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LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Product Features
3.3V Operation (5V tolerant) LPC Interface
- Multiplexed Command, Address and Data Bus - Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems
Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes
Keyboard Controller
- - - - - - - - - - 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 256 Bytes of Data RAM Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface Asynchronous Access to Two Data Registers and One Status Register Supports Interrupt and Polling Access 8 Bit Counter Timer Port 92 Support Fast Gate A20 and KRESET Outputs
ACPI 1.0b/2.0 Compliant Programmable Wake-up Event Interface PC99a/PC2001 Compliant General Purpose Input/Output Pins (13) Fan Tachometer Inputs (2) Green and Yellow Power LEDs ISA Plug-and-Play Compatible Register Set Motherboard GLUE Logic
- - - - - - - - - - - 5V Reference Generation 5V Standby Reference Generation IDE Reset/Buffered PCI Reset Outputs Power OK Signal Generation Power Sequencing Power Supply Turn On Circuitry Resume Reset Signal Generation Hard Drive Front Panel LED Voltage Translation for DDC to VGA Monitor SMBus Isolation Circuitry CNR Dynamic Down Control
Serial Ports
- Two Full Function Serial Ports - High Speed 16C550A Compatible UART with Send/Receive 16-Byte FIFOs - Supports 230k and 460k Baud - Programmable Baud Rate Generator - Modem Control Circuitry - 480 Address and 15 IRQ Options
Infrared Port
- - - - - - Multiprotocol Infrared Interface 32-Byte Data FIFO IrDA 1.0 Compliant SHARP ASK IR HP-SIR 480 Address, Up to 15 IRQ and Three DMA Options
,
2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller - Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core - Supports One Floppy Drive - Configurable Open Drain/Push-Pull Output Drivers - Supports Vertical Recording Format
16-Byte Data FIFO
- 100% IBM Compatibility - Detects All Overrun and Underrun Conditions
Multi-Mode Parallel Port with ChiProtect
- Standard Mode IBM PC/XT PC/AT, and PS/2 Compatible Bi-directional Parallel Port - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - IEEE 1284 Compliant Enhanced Capabilities Port (ECP) - ChiProtect Circuitry for Protection - 960 Address, Up to 15 IRQ and Three DMA Options
Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption
- DMA Enable Logic - Data Rate and Drive Control Registers
480 Address, Up to Eight IRQ and Three DMA Options
Interrupt Generating Registers
- Registers Generate IRQ1 - IRQ15 on Serial IRQ Interface.
XOR-Chain Board Test 128 Pin MQFP Package, 3.2 mm Footprint
SMSC LPC47M172
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
ORDERING INFORMATION
Order Number(s): LPC47M172-NR for 128 MQFP (3.2mm footprint) package
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Copyright (c) SMSC 2004. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
LPC47M172 Datasheet Revision History
REVISION LEVEL AND DATE Rev. 02-27-04 Rev. 02-27-04 Rev. 02-27-04 SECTION/FIGURE/ENTRY Table 12.2 - S3-S5 Standby Current, page 201 Ordering Information Table 6.1 - Super I/O Block Logical Device Number and Addresses, page 33 Chapter 1 - General Description, page 12 Chapter 12 - Electrical Characteristics, page 196 Section 3.1 - Buffer Name Descriptions, page 23 Table 3.1 - LPC47M172 Pin Description, page 15 Table 6.1 - Super I/O Block Logical Device Number and Addresses, page 33 Table 7.31 - Voltage Translation DDC Pins, page 137 Figure 7.10 - VGA DDC Voltage Translation Circuit, page 139 Table 7.34 - SMBus Isolation Pins, page 139 Figure 7.11 - SMBUS Isolation Circuit, page 140 Table 12.1 - Operational DC Characteristics, page 196 Table 7.7 - Programming for Configuration Register B (Bits 5:3), page 106; Table 7.8 Programming for Configuration Register B (Bits 2:0), page 106 Table 11.2 - LPC47M172 Configuration Register Summary, page 178 Table 11.3 - Chip Level Registers, page 180 CORRECTION Added note above table. Added. Revised heading to include "standard SMSC" and "non-standard SMSC" register sets. Revised General Description adding AMITM BIOS to keyboard interface. Lead Temperature Range, lead and leadfree; reference to spec name J-STD-020B. Added I0_SW. Buffer names revised for pins 87 - 90, 113 - 116. Note 8 under table revised. Added table. Replaced buffer IOD8 with IO_SW. Revised figure. Replaced buffer IOD8 with IO_SW. First paragraph under table revised. Revised figure. Added IO_SW buffer and description; updated parameters for Icc and Itr. Titles added to tables.
Rev. 02-26-04 Rev. 02-23-04 Rev. 02-20-04 Rev. 02-20-04
Rev. 02-20-04 Rev. 02-20-04 Rev. 02-20-04 Rev. 02-20-04 Rev. 02-20-04 Rev. 02-20-04 Rev. 02-20-04
Rev. 02-20-04 Rev. 02-20-04
Rev. 02-20-04 Rev. 02-20-04 Rev. 02-20-04 Rev. 02-20-04 Rev. 02-20-04 Rev. 02-20-04
Chapter 2 - Pin Layout, page 13 Table 3.1 - LPC47M172 Pin Description, page 15 Chapter 8 Power Control Runtime Registers, page 151 Chapter 9 GPIO Runtime Registers, page 158 Chapter 10 Runtime Register Block Runtime Registers, page 162 Table 11.3 - Chip Level Registers, page 180
Value of TEST 7 reg for LD_NUM=1 changed to 0x01. Definition of TEST 7 value: Default = 0x00 (when pin 117 is NC), 0x01 (when pin 117 is connected to VTR) on VCC POR, VTR POR, and HARD RESET Note for pin 117 No Connect Pin 117, Pin 117 described in Note 11. Table added. Table added. Added paragraph describing runtime registers tables. Register 0x29
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
Table Of Contents
LPC47M172 Datasheet Revision History ................................................................................................. 3
Chapter 1 Chapter 2 Chapter 3
3.1 3.2 3.3 3.4
General Description.............................................................................................................. 12 Pin Layout ............................................................................................................................ 13 Description of Pin Functions ................................................................................................ 15
Buffer Name Descriptions ..........................................................................................................................23 Pins With Internal Resistors .......................................................................................................................24 Pins That Require External Resistors.........................................................................................................24 Default State of Pins...................................................................................................................................25
Chapter 4 Chapter 5
Block Diagram ...................................................................................................................... 29 Power and Clock Functionality............................................................................................. 30
5.1 3 Volt Operation / 5 Volt Tolerance ............................................................................................................30 5.2 VCC Power ................................................................................................................................................30 5.3 VTR Power.................................................................................................................................................30 5.3.1 Trickle Power Functionality .................................................................................................................31 5.4 V5P0_STBY Power ....................................................................................................................................31 5.5 32.768 kHz Trickle Clock Input...................................................................................................................31 5.5.1 Indication of 32KHZ Clock...................................................................................................................31 5.6 14.318 MHz Clock Input .............................................................................................................................32 5.7 Internal PWRGOOD ...................................................................................................................................32 5.8 Maximum Current Values...........................................................................................................................32 5.9 Power Management Events (PME/SCI) .....................................................................................................32
Chapter 6
Functional Description.......................................................................................................... 33
6.1 Super I/O Registers....................................................................................................................................33 6.2 Host Processor Interface (LPC) .................................................................................................................34 6.3 LPC Interface .............................................................................................................................................34 6.3.1 LPC Interface Signal Definition ...........................................................................................................34 6.3.2 LPC Cycles .........................................................................................................................................34 6.3.3 Field Definitions...................................................................................................................................34 6.3.4 NLFRAME Usage................................................................................................................................35 6.3.5 I/O Read and Write Cycles..................................................................................................................35 6.3.6 DMA Read and Write Cycles ..............................................................................................................35 6.3.7 DMA Protocol ......................................................................................................................................35 6.3.8 Power Management ............................................................................................................................36 6.3.9 SYNC Protocol ....................................................................................................................................36 6.3.10 I/O and DMA START Fields.............................................................................................................37 6.3.11 LPC Transfers .................................................................................................................................37 6.4 Floppy Disk Controller ................................................................................................................................38 6.4.1 FDC Configuration Registers ..............................................................................................................38 6.4.2 FDC Internal Registers........................................................................................................................38 6.4.3 Status Register A (SRA) .....................................................................................................................39 6.4.4 Status Register B (SRB) .....................................................................................................................40 6.4.5 Digital Output Register (DOR).............................................................................................................42 6.4.6 Tape Drive Register (TDR) .................................................................................................................43 6.4.7 Data Rate Select Register (DSR)........................................................................................................44 6.4.8 Main Status Register...........................................................................................................................46 6.4.9 Data Register (FIFO)...........................................................................................................................47 6.4.10 Digital Input Register (DIR)..............................................................................................................48 6.4.11 Configuration Control Register (CCR) .............................................................................................49 6.4.12 Status Register Encoding ................................................................................................................50 6.5 Modes of Operation....................................................................................................................................52 6.5.1 PC/AT Mode .......................................................................................................................................52 6.5.2 PS/2 Mode ..........................................................................................................................................52 6.5.3 Model 30 Mode ...................................................................................................................................52 6.6 DMA Transfers ...........................................................................................................................................52 6.7 Controller Phases.......................................................................................................................................53 6.7.1 Command Phase ................................................................................................................................53 6.7.2 Execution Phase .................................................................................................................................53
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
6.8 Data Transfer Termination .........................................................................................................................54 6.9 Result Phase..............................................................................................................................................54 6.10 Command Set/Descriptions ....................................................................................................................54 6.10.1 Instruction Set..................................................................................................................................57 6.11 Data Transfer Commands ......................................................................................................................63 6.11.1 Read Data .......................................................................................................................................63 6.12 Read Deleted Data .................................................................................................................................64 6.13 Read A Track..........................................................................................................................................65 6.14 Write Data...............................................................................................................................................66 6.15 Write Deleted Data .................................................................................................................................66 6.16 Verify ......................................................................................................................................................66 6.17 Format A Track .......................................................................................................................................67 6.18 Control Commands.................................................................................................................................69 6.18.1 Read ID ...........................................................................................................................................69 6.18.2 Recalibrate ......................................................................................................................................69 6.18.3 Seek ................................................................................................................................................69 6.19 Sense Interrupt Status ............................................................................................................................70 6.20 Sense Drive Status .................................................................................................................................71 6.21 Specify....................................................................................................................................................71 6.22 Configure ................................................................................................................................................71 6.22.1 Configure Default Values.................................................................................................................71 6.23 Version ...................................................................................................................................................72 6.24 Relative Seek .........................................................................................................................................72 6.25 Perpendicular Mode................................................................................................................................73 6.26 Lock ........................................................................................................................................................74 6.27 Enhanced DUMPREG ............................................................................................................................75 6.27.1 Compatibility ....................................................................................................................................75 6.28 Serial Port (UART)..................................................................................................................................75 6.28.1 Register Description ........................................................................................................................75 6.28.2 Receive Buffer Register (RB) ..........................................................................................................76 6.28.3 Transmit Buffer Register (TB)..........................................................................................................76 6.28.4 Interrupt Enable Register (IER) .......................................................................................................76 6.28.5 FIFO Control Register (FCR)...........................................................................................................77 6.28.6 Interrupt Identification Register (IIR)................................................................................................77 6.28.7 Line Control Register (LCR) ............................................................................................................79 6.28.8 Modem Control Register (MCR) ......................................................................................................80 6.28.9 Line Status Register (LSR) ..............................................................................................................81 6.28.10 Modem Status Register (MSR)........................................................................................................82 6.28.11 Scratchpad Register (SCR) .............................................................................................................83 6.29 Programmable Baud Rate Generator (And Divisor Latches DLH, DLL) .................................................83 6.29.1 Effect Of The Reset on Register File ...............................................................................................84 6.29.2 FIFO Interrupt Mode Operation .......................................................................................................84 6.29.3 FIFO Polled Mode Operation...........................................................................................................85
Chapter 7
Notes On Serial Port Operation ........................................................................................... 89
7.1 FIFO Mode Operation: ...............................................................................................................................89 7.1.1 General ...............................................................................................................................................89 7.1.2 TX and RX FIFO Operation.................................................................................................................89 7.2 Infrared Interface ........................................................................................................................................90 7.3 Parallel Port................................................................................................................................................90 7.4 IBM XT/AT Compatible, Bi-Directional and EPP Modes.............................................................................92 7.4.1 Data Port .............................................................................................................................................92 7.4.2 Status Port ..........................................................................................................................................92 7.4.3 Control Port .........................................................................................................................................93 7.4.4 EPP Address Port ...............................................................................................................................94 7.4.5 EPP Data Port 0..................................................................................................................................94 7.4.6 EPP Data Port 1..................................................................................................................................94 7.4.7 EPP Data Port 2..................................................................................................................................94 7.4.8 EPP Data Port 3..................................................................................................................................95 7.5 EPP 1.9 Operation .....................................................................................................................................95 7.5.1 Software Constraints...........................................................................................................................95
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
7.6 EPP 1.9 Write.............................................................................................................................................95 7.7 EPP 1.9 Read ............................................................................................................................................96 7.8 EPP 1.7 Operation .....................................................................................................................................96 7.8.1 Software Constraints...........................................................................................................................96 7.9 EPP 1.7 Write.............................................................................................................................................97 7.10 EPP 1.7 Read .........................................................................................................................................97 7.10.1 Extended Capabilities Parallel Port .................................................................................................98 7.10.2 Vocabulary.......................................................................................................................................98 7.11 ECP Implementation Standard ...............................................................................................................99 7.11.1 Description.......................................................................................................................................99 7.12 Register Definitions...............................................................................................................................100 7.12.1 Data and ecpAFifo Port .................................................................................................................101 7.12.2 Device Status Register (dsr)..........................................................................................................102 7.12.3 Device Control Register (dcr) ........................................................................................................102 7.12.4 CFIFO (Parallel Port Data FIFO) ...................................................................................................103 7.12.5 ECPDFIFO (ECP Data FIFO) ........................................................................................................103 7.12.6 tFifo (Test FIFO Mode) ..................................................................................................................103 7.12.7 cnfgA (Configuration Register A) ...................................................................................................104 7.12.8 cnfgB (Configuration Register B) ...................................................................................................104 7.12.9 ecr (Extended Control Register) ....................................................................................................104 7.13 Operation..............................................................................................................................................107 7.13.1 Mode Switching/Software Control..................................................................................................107 7.14 ECP Operation .....................................................................................................................................107 7.15 Termination from ECP Mode ................................................................................................................108 7.16 Command/Data.....................................................................................................................................108 7.17 Data Compression ................................................................................................................................108 7.18 Pin Definition ........................................................................................................................................108 7.19 LPC Connections..................................................................................................................................109 7.20 Interrupts ..............................................................................................................................................109 7.21 FIFO Operation.....................................................................................................................................109 7.21.1 DMA Transfers ..............................................................................................................................110 7.21.2 DMA Mode - Transfers from the FIFO to the Host.........................................................................110 7.21.3 Programmed I/O Mode or Non-DMA Mode ...................................................................................110 7.21.4 Programmed I/O - Transfers from the FIFO to the Host ................................................................110 7.21.5 Programmed I/O - Transfers from the Host to the FIFO ................................................................111 7.22 Power Management..............................................................................................................................111 7.23 Serial IRQ .............................................................................................................................................111 7.23.1 Timing Diagrams For SER_IRQ Cycle ..........................................................................................111 7.23.2 SER_IRQ Cycle Control ................................................................................................................112 7.23.3 SER_IRQ Data Frame...................................................................................................................113 7.23.4 Stop Cycle Control.........................................................................................................................113 7.23.5 Latency ..........................................................................................................................................114 7.23.6 EOI/ISR Read Latency ..................................................................................................................114 7.23.7 AC/DC Specification Issue ............................................................................................................114 7.23.8 Reset and Initialization ..................................................................................................................114 7.24 Interrupt Generating Registers .............................................................................................................114 7.25 8042 Keyboard Controller Description ..................................................................................................115 7.25.1 Keyboard Interface ........................................................................................................................115 7.25.2 Keyboard Data Write .....................................................................................................................116 7.25.3 Keyboard Data Read .....................................................................................................................116 7.25.4 Keyboard Command Write ............................................................................................................116 7.25.5 Keyboard Status Read ..................................................................................................................116 7.25.6 CPU-to-Host Communication ........................................................................................................116 7.25.7 Host-to-CPU Communication ........................................................................................................116 7.25.8 KIRQ..............................................................................................................................................116 7.25.9 MIRQ .............................................................................................................................................117 7.25.10 External Keyboard and Mouse Interface .......................................................................................117 7.25.11 Keyboard Power Management ......................................................................................................117 7.25.12 Soft Power Down Mode.................................................................................................................117 7.25.13 Hard Power Down Mode ...............................................................................................................117
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 6 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
7.25.14 Interrupts .......................................................................................................................................118 7.25.15 Memory Configurations .................................................................................................................118 7.25.16 Register Definitions .......................................................................................................................118 7.25.17 External Clock Signal ....................................................................................................................119 7.25.18 Default Reset Conditions ...............................................................................................................119 7.25.19 GateA20 and Keyboard Reset.......................................................................................................119 7.26 Port 92 Fast Gatea20 and Keyboard Reset..........................................................................................119 7.26.1 Port 92 Register.............................................................................................................................119 7.26.2 Keyboard and Mouse PME Generation .........................................................................................123 7.27 General Purpose I/O.............................................................................................................................124 7.27.1 GPIO Pins .....................................................................................................................................125 7.27.2 Description.....................................................................................................................................125 7.27.3 GPIO Control .................................................................................................................................126 7.27.4 GPIO Operation.............................................................................................................................127 7.27.5 GPIO PME Functionality................................................................................................................128 7.27.6 Either Edge Triggered Interrupts ...................................................................................................128 7.28 PME Support ........................................................................................................................................128 7.28.1 `Wake on Specific Key' Option.......................................................................................................129 7.29 Fan Monitoring......................................................................................................................................130 7.29.1 Fan Tachometer Inputs .................................................................................................................131 7.29.2 Detection of a Stalled Fan .............................................................................................................131 7.30 Hard Drive and Power LED Logic .........................................................................................................132 7.30.1 Hard Drive Front Panel LED (Red) ................................................................................................132 7.30.2 Yellow and Green Power LED Pins ...............................................................................................133 7.31 Power Generation (5V) .........................................................................................................................134 7.31.1 Reference Pins ..............................................................................................................................134 7.31.2 5V Main Reference Generation .....................................................................................................135 7.31.3 5V Standby Reference Generation................................................................................................135 7.31.4 Reference Timings ........................................................................................................................136 7.32 IDE Reset Output Pin ...........................................................................................................................136 7.33 PCI Reset Output Pins..........................................................................................................................136 7.34 Voltage Translation Circuit....................................................................................................................137 7.35 SMBus Isolation Circuitry......................................................................................................................139 7.36 PS_ON Logic ........................................................................................................................................141 7.37 PWRGD_3V Logic ................................................................................................................................141 7.38 SCK_BJT_GATE Output ......................................................................................................................143 7.39 Backfeed Cut and Latched Backfeed Cut Circuitry ...............................................................................144 7.40 Resume Reset Logic ............................................................................................................................149 7.41 CNR Logic ............................................................................................................................................149
Chapter 8 Chapter 9 Chapter 10 Chapter 11
Power Control Runtime Registers...................................................................................... 151 GPIO Runtime Registers.................................................................................................... 158 Runtime Register Block Runtime Registers ....................................................................... 162 Configuration ...................................................................................................................... 173
11.1 System Elements..................................................................................................................................173 11.1.1 Primary Configuration Address Decoder .......................................................................................173 11.1.2 Entering the Configuration State....................................................................................................173 11.1.3 Exiting the Configuration State ......................................................................................................173 11.1.4 Configuration Sequence ................................................................................................................174 11.1.5 Enter Configuration Mode..............................................................................................................174 11.1.6 Configuration Mode .......................................................................................................................174 11.1.7 Exit Configuration Mode ................................................................................................................174 11.1.8 Programming Example ..................................................................................................................175 11.2 Chip Level (Global) Control/Configuration Registers[0x00-0x2F] .........................................................180 11.3 Logical Device Configuration/Control Registers [0x30-0xFF] ...............................................................183 11.4 Logical Device I/O Address ..................................................................................................................187 11.5 Logical Device Configuration Registers ................................................................................................190
Chapter 12
12.1 12.2 12.3
Electrical Characteristics .................................................................................................... 196
Maximum Guaranteed Ratings .............................................................................................................196 Operational DC Characteristics ............................................................................................................196 Standby Power Requirements ..............................................................................................................201
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
12.4
Capacitance Values for Pins.................................................................................................................202
Chapter 13
Timing Diagrams ................................................................................................................203
13.1 ECP Parallel Port Timing ......................................................................................................................212 13.1.1 Parallel Port FIFO (Mode 101).......................................................................................................212 13.1.2 ECP Parallel Port Timing ...............................................................................................................212 13.1.3 Forward-Idle ..................................................................................................................................212 13.1.4 Forward Data Transfer Phase .......................................................................................................212 13.1.5 Reverse-Idle Phase .......................................................................................................................212 13.1.6 Reverse Data Transfer Phase .......................................................................................................212 13.1.7 Output Drivers ...............................................................................................................................213
Chapter 14 Chapter 15 Chapter 16
Package Outline ................................................................................................................. 224 Board Test Mode................................................................................................................225 Reference Documents........................................................................................................ 227
List Of Figures
Figure 2.1 - LPC47M172 Pin Layout ............................................................................................................................13 Figure 4.1 - LPC47M172 Block Diagram......................................................................................................................29 Figure 7.1 - NKBDRST Circuit....................................................................................................................................121 Figure 7.2 - Keyboard Latch.......................................................................................................................................122 Figure 7.3 - Mouse Latch ...........................................................................................................................................122 Figure 7.4 - GPIO Function Illustration.......................................................................................................................127 Figure 7.5 - Fan Tachometer Input and Clock Source ...............................................................................................131 Figure 7.6 - NHD_LED Circuit ....................................................................................................................................133 Figure 7.7 - YLW_LED/GRN_LED Circuit ..................................................................................................................134 Figure 7.8 - REF5V Circuit .........................................................................................................................................135 Figure 7.9 - REF5V_STBY.........................................................................................................................................136 Figure 7.10 - VGA DDC Voltage Translation Circuit...................................................................................................139 Figure 7.11 - SMBUS Isolation Circuit........................................................................................................................140 Figure 7.12 - PWRGD_3V Circuit, Discrete Implementation ......................................................................................142 Figure 7.13 - PWRGD_3V Circuit in LPC47M172 ......................................................................................................142 Figure 7.14 - NFPRST Timing....................................................................................................................................143 Figure 7.15 - SCK_BJT_Gate Circuit .........................................................................................................................144 Figure 7.16 - Backfeed Cut and Latched Backfeed Cut Circuit ..................................................................................145 Figure 7.17 - Latched Backfeed Cut Power Up Sequence.........................................................................................146 Figure 7.18 - Latched Backfeed Cut Sequence 1 ......................................................................................................146 Figure 7.19 - Latched Backfeed Cut Sequence 2 ......................................................................................................147 Figure 7.20 - Latched Backfeed Cut Flowchart ..........................................................................................................148 Figure 7.21 - CNR Circuit ...........................................................................................................................................150 Figure 13.1 - Power-Up Timing ..................................................................................................................................204 Figure 13.2 - Input Clock Timing ................................................................................................................................205 Figure 13.3 - PCI Clock Timing ..................................................................................................................................205 Figure 13.4 - Reset Timing.........................................................................................................................................205 Figure 13.5 - Output Timing Measurement Conditions, LPC Signals .........................................................................206 Figure 13.6 - Input Timing Measurement Conditions, LPC Signals............................................................................206 Figure 13.7 - I/O Write................................................................................................................................................206 Figure 13.8 - I/O Read ...............................................................................................................................................207 Figure 13.9 - DMA Request Assertion through NLDRQ .............................................................................................207 Figure 13.10 - DMA Write (First Byte) ........................................................................................................................207 Figure 13.11 - DMA Read (First Byte)........................................................................................................................207 Figure 13.12 - Floppy Disk Drive Timing (At Mode Only) ...........................................................................................208 Figure 13.13 - EPP 1.9 Data or Address Write Cycle.................................................................................................209 Figure 13.14 - EPP 1.9 Data or Address Read Cycle ................................................................................................210 Figure 13.15 - EPP 1.7 Data or Address Write Cycle.................................................................................................211 Figure 13.16 - EPP 1.7 Data or Address Read Cycle ................................................................................................211 Figure 13.17 - Parallel Port FIFO Timing ...................................................................................................................213 Figure 13.18 - ECP Parallel Port Forward Timing ......................................................................................................214 Figure 13.19 - ECP Parallel Port Reverse Timing ......................................................................................................215 Figure 13.20 - Setup and Hold Time ..........................................................................................................................216
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
Figure 13.21 - Serial Port Data...................................................................................................................................216 Figure 13.22 - Keyboard/Mouse Receive/Send Data Timing .....................................................................................217 Figure 13.23 - Fan Tachometer Input Timing .............................................................................................................218 Figure 13.24 - Power Led Output Timing ...................................................................................................................218 Figure 13.25 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Up Before VCC5V/ V_5P0_STBY ...............219 Figure 13.26 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Up Before VCC/VTR ...............219 Figure 13.27 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Down Before VCC5V/ V_5P0_STBY...........220 Figure 13.28 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Down Before VCC/VTR...........220 Figure 13.29 - Rise, Fall and Propagation Timings ....................................................................................................221 Figure 13.30 - Reseme Reset Sequence ...................................................................................................................223 Figure 14.1 - 128 Pin MQFP Package Outline, 14x20x2.7 Body, 3.2mm Footprint....................................................224 Figure 15.1 - Example XOR Chain Circuitry...............................................................................................................225
List Of Tables
Table 3.1 - LPC47M172 Pin Description ......................................................................................................................15 Table 3.2 - Pins with Internal Resistors........................................................................................................................24 Table 3.3 - Pins that Require External Resistors..........................................................................................................24 Table 3.4 - Default State of Pins ..................................................................................................................................26 Table 6.1 - Super I/O Block Logical Device Number and Addresses ...........................................................................33 Table 6.2 - Status, Data and Control Registers............................................................................................................38 Table 6.3 - Internal 2 Drive Decode - Normal...............................................................................................................42 Table 6.4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped ...................................................................................43 Table 6.5 - Tape Select Bits .........................................................................................................................................43 Table 6.6 - Drive Type ID .............................................................................................................................................44 Table 6.7 - Precompensation Delays ...........................................................................................................................45 Table 6.8 - Data Rates .................................................................................................................................................45 Table 6.9 - DRVDEN Mapping .....................................................................................................................................46 Table 6.10 - Default Precompensation Delays .............................................................................................................46 Table 6.11 - FIFO Service Delay..................................................................................................................................47 Table 6.12 - Status Register 0 .....................................................................................................................................50 Table 6.13 - Status Register 1 .....................................................................................................................................50 Table 6.14 - Status Register 2 .....................................................................................................................................51 Table 6.15 - Status Register 3 .....................................................................................................................................51 Table 6.16 - Description of Command Symbols ...........................................................................................................55 Table 6.17 - Instruction Set ..........................................................................................................................................57 Table 6.18 - Sector Sizes .............................................................................................................................................63 Table 6.19 - Effects of MT and N Bits ..........................................................................................................................64 Table 6.20 - Skip Bit vs Read Data Command.............................................................................................................64 Table 6.21 - Skip Bit vs. Read Deleted Data Command ..............................................................................................65 Table 6.22 - Result Phase Table..................................................................................................................................65 Table 6.23 - Verify Command Result Phase Table ......................................................................................................67 Table 6.24 - Typical Values for Formatting ..................................................................................................................68 Table 6.25 - Interrupt Identification...............................................................................................................................70 Table 6.26 - Drive Control Delays (ms) ........................................................................................................................71 Table 6.27 - Effects of WGATE and GAP Bits .............................................................................................................74 Table 6.28 - Addressing the Serial Port .......................................................................................................................75 Table 6.29 - Interrupt Control Table .............................................................................................................................78 Table 6.30 - Baud Rates ..............................................................................................................................................85 Table 6.31 - Reset Function Table ...............................................................................................................................86 Table 32 - Register Summary for an Individual UART Channel ...................................................................................87 Table 7.1 - Parallel Port Connector ..............................................................................................................................92 Table 7.2 - EPP Pin Descriptions .................................................................................................................................97 Table 7.3 - ECP Pin Descriptions...............................................................................................................................100 Table 7.4 - ECP Register Definitions..........................................................................................................................101 Table 7.5 - Mode Descriptions ...................................................................................................................................101 Table 7.6 - Extended Control Register .......................................................................................................................106 Table 7.7 - Programming for Configuration Register B (Bits 5:3) ...............................................................................106 Table 7.8 - Programming for Configuration Register B (Bits 2:0) ...............................................................................106
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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Table 7.9 - Channel/Data Commands supported in ECP mode .................................................................................108 Table 7.10 - I/O Address Map ....................................................................................................................................115 Table 7.11 - Host Interface Flags ...............................................................................................................................116 Table 7.12 - Status Register ......................................................................................................................................118 Table 7.13 - Keyboard and Mouse Pin/Register Reset Values ..................................................................................119 Table 7.14 - Keyboard Port 92 Register.....................................................................................................................120 Table 7.15 - nA20M Truth Table ................................................................................................................................121 Table 7.16 - GPIO Summary......................................................................................................................................125 Table 7.17 - General Purpose I/O Port Assignments .................................................................................................126 Table 7.18 - GPIO Configuration Summary ...............................................................................................................126 Table 7.19 - GPIO Read/Write Behavior ....................................................................................................................127 Table 7.20 - Hard Drive Front Panel Pins ..................................................................................................................132 Table 7.21 - nHD_LED Truth Table............................................................................................................................132 Table 7.22 - LED Pins ................................................................................................................................................133 Table 7.23 - LED Truth Table.....................................................................................................................................133 Table 7.24 - Reference Generation Pins....................................................................................................................134 Table 7.25 - REF5V ...................................................................................................................................................135 Table 7.26 - REF5V_STBY ........................................................................................................................................135 Table 7.27 - nIDE_RSTDRV Pin ................................................................................................................................136 Table 7.28 - nIDE_RSTDRV Truth Table ...................................................................................................................136 Table 7.29 - nPCIRST_OUT Pins ..............................................................................................................................137 Table 7.30 - nPCIRST_OUT and nPCIRST_OUT2 Truth Table ................................................................................137 Table 7.31 - Voltage Translation DDC Pins ...............................................................................................................137 Table 7.32 - VGA DDCSDA Voltage Translation Logic ..............................................................................................138 Table 7.33 - VGA DDCSCL Voltage Translation Logic ..............................................................................................138 Table 7.34 - SMBus Isolation Pins .............................................................................................................................139 Table 7.35 - SMB_CLK Isolation Logic ......................................................................................................................140 Table 7.36 - SMB_DAT Isolation Logic ......................................................................................................................140 Table 7.37 - nPS_ON, nCPU_PRESENT and nSLP_S3 Pins ...................................................................................141 Table 7.38 - nPS_ON Truth Table..............................................................................................................................141 Table 7.39 - PWRGD_3V, nFPRST and PWRGD_PS Pins .......................................................................................141 Table 7.40 - PWRGD_3V Truth Table........................................................................................................................142 Table 7.41 - SCK_BJT_GATE Pin .............................................................................................................................143 Table 7.42 - SCK_BJT_GATE Truth Table ................................................................................................................143 Table 7.43 - nBACKFEED_CUT and LATCHED_BF_CUT Pins ................................................................................144 Table 7.44 - nBACKFEED_CUT Truth Table .............................................................................................................144 Table 7.45 - LATCHED_BF_CUT Truth Table ...........................................................................................................145 Table 7.46 - Latched Backfeed Cut Power Up Sequence Timing ..............................................................................146 Table 7.47 - Latched Backfeed Cut Sequence 1 and 2 Timing ..................................................................................147 Table 7.48 - nRSMRST Pin........................................................................................................................................149 Table 7.49 - CNR Pins ...............................................................................................................................................149 Table 7.50 - CNR Logic Truth Table ..........................................................................................................................150 Table 8.1 - Power Control Runtime Registers Summary, LD_NUM Bit = 0................................................................151 Table 8.2 - Power Control Runtime Registers Description, LD_NUM Bit = 0 .............................................................152 Table 9.1 - GPIO Runtime Registers Summary, LD_NUM = 0...................................................................................158 Table 9.2 - GPIO Runtime Registers Description, LD_NUM = 0 ................................................................................159 Table 10.1 - Runtime Register Block Runtime Registers Summary ...........................................................................162 Table 10.2 - Runtime Register Block Runtime Registers Description ........................................................................163 Table 11.1 - LPC47M172 Configuration Registers Summary, LD_NUM bit = 0 .........................................................176 Table 11.2 - LPC47M172 Configuration Register Summary, LD_NUM=1..................................................................178 Table 11.3 - Chip Level Registers ..............................................................................................................................180 Table 11.4 - Logical Device Registers........................................................................................................................183 Table 11.5 - Primary Interrupt Select Configuration Register Description ..................................................................185 Table 11.6 - DMA Channel Select Configuration Register Description ......................................................................185 Table 11.7 - Logical Device I/O Address, LD_NUM Bit = 0 ........................................................................................187 Table 11.8 - Logical Device I/O Address, LD_NUM Bit = 1 .......................................................................................188 Table 11.9 - Floppy Disk Controller Logical Device Configuration Registers .............................................................190 Table 11.10 - Serial Port 2 Logical Device Configuration Registers...........................................................................191 Table 11.11 - Parallel Port Logical Device Configuration Registers ...........................................................................192 Table 11.12 - Serial Port 1 Logical Device Configuration Registers...........................................................................193
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 10 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
Table 11.13 - Keyboard Logical Device Configuration Registers ...............................................................................194 Table 11.14 - Power Control/Runtime Register Block Logical Device Configuration Registers .................................194 Table 12.1 - Operational DC Characteristics..............................................................................................................196 Table 12.2 - S3-S5 Standby Current ..........................................................................................................................201 Table 13.1 - nIDE_RSTDRV Timing...........................................................................................................................221 Table 13.2 - nPCIRST_OUT and nPCIRST_OUT2 Timing ........................................................................................221 Table 13.3 - PS_ON Timing .......................................................................................................................................221 Table 13.4 - SCK_BJT_GATE Timing........................................................................................................................222 Table 13.5 - PWRGD_3V Timing ...............................................................................................................................222 Table 13.6 - CNR CODEC Down Enable Timing .......................................................................................................222 Table 13.7 - Resume Reset Timing............................................................................................................................223 Table 14.1 - 128 Pin MQFP Package Parameters .....................................................................................................224 Table 15.1 - XOR Test Pattern Example....................................................................................................................226
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
Chapter 1
General Description
The LPC47M172 is a 3.3V (5V tolerant) PC99a/PC2001 compliant Advanced I/O controller for Desktop PCs. The device, which implements the Low Pin Count (LPC) interface, includes I/O functionality as well as Motherboard GLUE logic into a 128-pin package. This is space saving solution on the motherboard resulting in lower cost. The LPC47M172 also provides 13 general purpose pins, which offer flexibility to the system designer, and two Fan Tachometer Inputs. The LPC47M172's LPC interface supports LPC I/O and DMA cycles. The LPC47M172 includes complete legacy I/O: a keyboard interface with AMITM BIOS; SMSC's true CMOS 765B floppy disk controller with advanced digital data separator; two 16C550A compatible UARTs; one Multi-Mode parallel port including ChiProtect circuitry plus EPP and ECP. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures; in addition, it provides data overflow and underflow protection. The SMSC's patented advanced digital data separator allows for ease of testing and use. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The LPC47M172 incorporates sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake up events as well as PME support. The PCC supports multiple low power-down modes. The LPC47M172 is ACPI 1.0b/2.0 compatible. The Motherboard GLUE logic includes various power management logic; including generation of nRSMRST, Power OK signal generation, 5V main and standby reference generation. There are also three LEDs to indicate power status and hard drive activity. The translation circuit converts 3.3V signals to 5V signals. Also included is SMBus main power well to resume power well isolation circuitry. The LPC47M172 supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47M172 may be reprogrammed through the internal configuration registers. There are up to 480 (960 for Parallel Port) I/O address location options, a Serialized IRQ interface, and three DMA channels. On chip, Interrupt Generating Registers enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface. The LPC47M172's Enhanced Digital Data Separator does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The LPC47M172 is register compatible with SMSC's proprietary 82077AA core. This device utilizes two selectable (see Chapter 2) register sets; (1) standard SMSC and (2) tailored for Intel reference designs. These register sets are detailed in Chapter 6 (Section 6.1).
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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Chapter 2
Pin Layout
IRTX2 IRRX2 nDCD2 nDTR2 nCTS2 VCC nRTS2 nDSR2 TXD2 RXD2 nRI2 NC/VTR (Note) DDCSDA_5V/GP20 DDCSDA_3V/GP22 DDCSCL_5V/GP21 DDCSCL_3V/GP23 GP17/FAN_TACH2 GP16/FAN_TACH1 VSS GP15 GP14 VTR GP13 GP12 GP11 GP10
MCLK MDAT KCLK KDAT GA20M VCC nKBDRST VSS nDSKCHG nHDSEL nRDATA nWRTPRT nTRK0 nWGATE nWDATA nSTEP nDIR nDS0 nMTR0 nINDEX DRVDEN1 DRVDEN0 nDCD nDSR RXD nRTS TXD nCTS VSS nDTR (XOR) VCC nRI SLCT PE BUSY nACK PD7 PD6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
LPC47M172 128 PIN QFP
nCDC_DWN_RST nCDC_DWN_ENAB/GP24 nAUD_LINK_RST nIO_PME TEST_EN F_CAP VSS YLW_LED GRN_LED VTR nRSMRST CLOCKI32 SMB_DAT_R SMB_DAT_M SMB_CLK_R SMB_CLK_M nSLP_S5 nSLP_S3 PWRGD_3V nCPU_PRESENT PWRGD_PS nPS_ON SCK_BJT_GATE LATCHED_BF_CUT VSS nBACKFEED_CUT VTR nFPRST nPCIRST_OUT2 nPCIRST_OUT REF5V_STBY V_5P0_STBY REF5V nSCSI nSECONDARY_HD nPRIMARY_HD nHD_LED CLOCKI
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
PD5 PD4 PD3 PD2 PD1 PD0 nERROR VSS nSLCTIN nINITP VCC nALF nSTROBE nLPCPD SER_IRQ nLDRQ PCI_CLK nLFRAME LAD3 VSS LAD2 VCC LAD1 LAD0 nPCI_RESET nIDE_RSTDRV
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Figure 2.1 - LPC47M172 Pin Layout
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
Note:
Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the LPC47M172. See Table 6.1 - Super I/O Block Logical Device Number and Addresses. The pin functions as follows:
The pin has an internal pull-down resistor that selects the non-standard SMSC (Intel Compatible) mode. To select this mode, the pin should be left unconnected. This configuration clears the LD_NUM bit to `0' and the associated functionality corresponds to the existing functionality in the part when the LD_NUM bit=0. Connecting this pin to VTR will select the standard SMSC mode of the logical device numbering. This configuration sets the LD_NUM bit to `1' and the associated functionality corresponds to the existing functionality in the part when the LD_NUM bit=1.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
Chapter 3
Description of Pin Functions
Table 3.1 - LPC47M172 Pin Description
PIN#
NAME (NOTE 1)
DESCRIPTION
BUFFER NAME (NOTE 2) PWR
PWR WELL (NOTE 3)
NOTES
POWER AND GROUND PINS (20) See Note 11 6,31, 49,60, 123 76,93, 107, 117
See Note
VCC
+3.3 Volt Main Supply Voltage (5)
VTR
+3.3 Volt Standby Supply Voltage (4) See
Note
PWR
11
71 8,29, 46,58, 78,96, 110 70 72
V_5P0_STBY VSS
+5 Volt Standby Supply Voltage. Ground (7)
PWR PWR
REF5V REF5V_STBY
97
F_CAP
65 91 52
CLOCKI CLOCKI32 nLPCPD
53
SER_IRQ
54
nLDRQ
55 56 57,59, 61,62
PCI_CLK nLFRAME LAD[3:0]
AO 5V Reference Output. Requires external pull-up to VCC5V. AO Highest System Standby Voltage. Requires external pull-up to V_5P0_STBY. Internal Regulator Filter Capacitor. This pin is a no connect. A filter capacitor can be placed on this pin if it is required by system board layout. CLOCKS (2) 14.318Mhz Clock Input IS 32.768kHz Clock Input IS PROCESSOR/HOST LPC INTERFACE (11) PCI_I Active low input Power Down signal indicates that the LPC47M172 should prepare for power to be shut-off on the LPC interface. Serial IRQ pin used with the PCI_CLK pin PCI_IO to transfer LPC47M172 interrupts to the host. PCI_O Active low output used for encoded DMA/Bus Master request for the LPC interface. 33.33 MHz PCI Clock input. PCI_ICLK PCI_I Active low input indicates start of new cycle and termination of broken cycle. PCI_IO Active high LPC I/O used for multiplexed command, address and data bus.
VCC VTR
VCC VTR VCC
4 5
VCC
VCC
VCC VCC VCC
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
PIN# 63
NAME (NOTE 1) nPCI_RESET
DESCRIPTION Active low input used as LPC Interface Reset. 3.3V and 5V buffered copy of PCI Reset signal is available on nPCIRST_OUT and nIDE_RSTDRV. These pins are listed under GLUE PINS. Power Management Event Output. This active low Power Management Event signal allows to request wakeup. This pin can be configured as Push-Pull Output. FDD INTERFACE (14) This input senses that the drive door is open or that the diskette has possibly been changed since the last drive selection. This input is inverted and read via bit 7 of I/O address 3F7H. The nDSKCHG bit also depends upon the state of the Force Disk Change bits in the Force Disk Change register (see Chapter 11 Configuration). Head Select Output. This high current output selects the floppy disk side for reading or writing. A logic "1" on this pin means side 0 will be accessed, while a logic "0" means side 1 will be accessed. Can be configured as an Open-Drain Output. Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data. This active low Schmitt Trigger input senses from the disk drive that a disk is write protected. Any write command is ignored. The nWRPRT bit also depends upon the state of the Force Write Protect bit in the FDD Option register (see the Configuration Registers section). This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the outermost track. Write Gate Output. This active low high current driver allows current to flow through the write head. It becomes active just prior to writing to the diskette. Can be configured as an Open-Drain Output. Write Disk Data Output. This active low high current driver provides the encoded data to the disk drive. Each falling edge causes a flux transition on the media. Can be configured as an Open-Drain Output.
BUFFER NAME (NOTE 2) PCI_I
PWR WELL (NOTE 3) VCC
NOTES
99
nIO_PME
OD8
VTR
9
nDSKCHG
IS
VCC
10
nHDSEL
O12
VCC
11
nRDATA
IS
VCC
12
nWRTPRT
IS
VCC
13
nTRK0
IS
VCC
14
nWGATE
O12
VCC
15
nWDATA
O12
VCC
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
PIN# 16
NAME (NOTE 1) nSTEP
DESCRIPTION
17
nDIR
18 19 20
nDS0 nMTR0 nINDEX
21
DRVDEN1
22
DRVDEN0
23
nDCD1
24
nDSR1
25
RXD1
Step Pulse Output. This active low high current driver issues a low pulse for each track-to-track movement of the head. Can be configured as an Open-Drain Output. O12 Step Direction Output. This high current low active output determines the direction of the head movement. A logic "1" on this pin means outward motion, while a logic "0" means inward motion. Can be configured as an Open-Drain Output. O12 Drive Select 0 Output. Can be configured as an Open-Drain Output. Motor On 0 Output. Can be configured as O12 an Open-Drain Output. IS This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. O12 Drive Density Select 1 Output. Indicates the drive and media selected. Can be configured as Open-Drain Output. O12 Drive Density Select 0 Output. Indicates the drive and media selected. Can be configured as Open-Drain Output. SERIAL PORT 1 INTERFACE (8) I Active low Data Carrier Detect input for the serial port. Handshake signal that notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD. I Active low Data Set Ready input for the serial port. Handshake signal that notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR. Receiver serial data input. IS
BUFFER NAME (NOTE 2) O12
PWR WELL (NOTE 3) VCC
NOTES
VCC
VCC VCC VCC
VCC
VCC
VCC
VCC
VCC
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
PIN# 26
NAME (NOTE 1) nRTS1
DESCRIPTION
27 28
TXD1 nCTS1
30
nDTR1
(XOR) 32 nRI1
118 119 120
nRI2 RXD2 TXD2
Active low Request to Send output for the Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of the Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). nRTS is forced inactive during loop mode operation. Transmit serial data output. O12 I Active low Clear to Send input for the serial port. Handshake signal that notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS. O8 Active low Data Terminal Ready output for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). nDTR is forced inactive during loop mode operation. XOR Chain Output. I Active low Ring Indicator input for the serial port. Handshake signal that notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR). A nRI signal state change from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nRI changes state. Note: Bit 6 of MSR is the complement of nRI. SERIAL PORT 2 INTERFACE (8) IPD Active low Ring Indicator input for serial port 2. See description for nRI1. Receiver serial data input. ISPD_400 Transmit serial data output. O12
BUFFER NAME (NOTE 2) O8
PWR WELL (NOTE 3) VCC
NOTES
VCC VCC
VCC
VTR
6
VTR VCC VCC
6, 10
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
PIN# 121 122 124 125
NAME (NOTE 1) nDSR2 nRTS2 nCTS2 nDTR2
DESCRIPTION
126
nDCD2
127 128 33
IRRX2 IRTX2 SLCT
34
PE
35
BUSY
36
nACK
37 38 39 40 41 42 43 44
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Active low Data Set Ready input for serial port 2. See description for nDSR1. O8 Active low Request to Send output for Serial Port 2. See description for nRTS1. IPD Active low Clear to Send input for serial port 2. See description for nCTS1. O8 Active low Data Terminal Ready output for serial port 2. See description for nDTR1. IPD Active low Data Carrier Detect input for serial port 2. See description for nDCD1. INFRARED INTERFACE (2) Infrared receive input. ISPD_400 Infrared transmit output. O12 PARALLEL PORT INTERFACE (17) I This high active input from the printer indicates that it has power on. Bit 4 of the Printer Status Register reads the SLCT input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. I Another status input from the printer, a high indicating that the printer is out of paper. Bit 5 of the Printer Status Register reads the PE input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. I This is a status input from the printer, a high indicating that the printer is not ready to receive new data. Bit 7 of the Printer Status Register is the complement of the BUSY input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. I A low active input from the printer indicating that it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the nACK input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Port Data 7 I/O IOP14 Port Data 6 I/O IOP14 Port Data 5 I/O IOP14 Port Data 4 I/O IOP14 Port Data 3 I/O IOP14 Port Data 2 I/O IOP14 Port Data 1 I/O IOP14 Port Data 0 I/O IOP14
BUFFER NAME (NOTE 2) IPD
PWR WELL (NOTE 3) VCC VCC VCC VCC
NOTES 10
10
VCC
10
VCC VCC VCC
10 9
VCC
VCC
VCC
VCC VCC VCC VCC VCC VCC VCC VCC
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
PIN# 45
NAME (NOTE 1) nERROR
DESCRIPTION
BUFFER NAME (NOTE 2)
47
nSLCTIN
48
nINITP
50
nALF
51
nSTROBE
1 2 3 4 5 7 64 66 67 68 69
MCLK MDAT KCLK KDAT GA20M nKBDRST nIDE_RSTDRV nHD_LED nPRIMARY_ HD nSECONDARY _HD nSCSI
I A low on this input from the printer indicates that there is an error condition at the printer. Bit 3 of the Printer Status register reads the nERR input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. OP14 This active low output selects the printer. This is the complement of bit 3 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be Configured as an Open-Drain Output. OP14 This output is bit 2 of the printer control register. This is used to initiate the printer when low. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be configured as an Open-Drain Output. OP14 This output goes low to cause the printer to automatically feed one line after each line is printed. The nALF output is the complement of bit 1 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be configured as an Open-Drain Output. OP14 An active low pulse on this output is used to strobe the printer data into the printer. The nSTROBE output is the complement of bit 0 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be configured as an Open-Drain Output. KEYBOARD/MOUSE INTERFACE (6) Mouse Clock I/O IOD24 Mouse Data I/O IOD24 Keyboard Clock I/O IOD24 Keyboard Data I/O IOD24 Gate A20 Open-Drain Output OD8 Keyboard Reset Open-Drain Output OD8 GLUE PINS (29) IDE Reset Output OD8 OD12 Hard Drive Front Panel LED Open-Drain Output IDE Primary Drive Active Input ISPU_400 IDE Secondary Drive Active Input SCSI Drive Active Input
Page 20
PWR WELL (NOTE 3) VCC
NOTES
VCC
VCC
VCC
VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
6 6 7 7 3 3
ISPU_400 ISPU_400
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
PIN# 73 74 75 77 79 80 81 82 83 84 85 86 87 88 89 90 92 100 101
NAME (NOTE 1) nPCIRST_OUT nPCIRST_OUT 2 nFPRST nBACKFEED_ CUT LATCHED_BF_ CUT SCK_BJT_ GATE nPS_ON PWRGD_PS
nCPU_PRESENT
DESCRIPTION Buffered PCI Reset Output Second Buffered PCI Reset Output Reset Input from Front Panel Open-Drain Output used for STR Circuitry Latched Backfeed Cut Output for STR Circuitry Open-Drain Gate Output for the SCK_BJT in Suspend-to-RAM Power Supply Turn-ON Open Drain Output Power Good Input from Power Supply CPU Present Input from Processor Power Good Output S3 Power State Input from South Bridge Input from South Bridge for Transitioning to the S5 Power State SMBus Clock Main SMBus Clock Resume SMBus Data Main SMBus Data Resume Resume Reset Output AC97 Link Reset Input AC97 Codec Down Enable Input. General Purpose I/O. GPIO can be configured as an open-drain output. AC97 Codec Down Reset Output. 3.3V DDC Clock General Purpose I/O. GPIO can be configured as an open-drain output. 5V DDC Clock General Purpose I/O. GPIO can be configured as an open-drain output. 3.3V DDC Data General Purpose I/O. GPIO can be configured as an open-drain output. 5V DDC Data General Purpose I/O. GPIO can be configured as an open-drain output. POWER LEDS (2) Green Power LED Open-Drain Output Yellow Power LED Open-Drain Output GENERAL PURPOSE I/O (8) General Purpose I/O. GPIO can be configured as an open-drain output.
BUFFER NAME (NOTE 2) OP14 OP14 ISPU_400 OD8 OP14 OD8 OD8 ISPU_400 ISPU_400 O8 IS_400 IS_400 IO_SW IO_SW IO_SW IO_SW O8 I IO12
PWR WELL (NOTE 3) VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR 6 3 3
NOTES
3
PWRGD_3V nSLP_S3 nSLP_S5 SMB_CLK_M SMB_CLK_R SMB_DAT_M SMB_DAT_R nRSMRST nAUD_LINK_ RST nCDC_DWN_ ENAB/GP24 nCDC_DWN_ RST DDCSCL_3V/ GP23 DDCSCL_5V/ GP21 DDCSDA_3V/ GP22 DDCSDA_5V/ GP20
102 113
O12 IO_SW/IS OD8 IO_SW/IS OD8 IO_SW/IS OD8 IO_SW/IS OD8
VTR VTR 3, 6, 8
114
VTR
3, 6, 8
115
VTR
3, 6, 8
116
VTR
3, 6, 8
94 95 103105
GRN_LED YLW_LED GP10-GP12
OD24 OD24 ISO8
VTR VTR VTR 6
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
PIN# 106, 108, 109 111
NAME (NOTE 1) GP13-GP15
DESCRIPTION General Purpose I/O. GPIO can be configured as an open-drain output. General Purpose I/O. GPIO can be configured as an open-drain output. Fan Tachometer 1 Input General Purpose I/O. GPIO can be configured as an open-drain output. Fan Tachometer 2 Input TEST (1) Test Enable Input for XOR-Chain test - the external pull-up or internal pull-down sets the strap value. The XOR output is the nDTR1 pin. NO CONNECT (1) See Note11 No Connect
BUFFER NAME (NOTE 2) IO8
PWR WELL (NOTE 3) VTR
NOTES 6
GP16/ FAN_TACH1 GP17/ FAN_TACH2
IO8
VTR
6
112
IO8
VTR
6
98
TEST_EN
IPD
VTR
117 Note 1:
NC
IPD
-
11
The "n" as the first letter of a signal name or the "#" as the suffix of a signal name indicates an "Active Low" signal. The primary and secondary functions on the pins are separated by "/". The buffer names are described in the "Buffer Name Descriptions" section. Open-drain pins should be pulled-up externally to supply shown in the power well column. The nIDE_RSTDRV, nHD_LED, DDCSDA_5V and DDCSCL_5V open-drain pins require external pull-ups to VCC5V. The nBACKFEED_CUT, SCK_BJT_GATE and nPS_ON open-drain pins require external pullups to V_5P0_STBY. Inputs with internal pull-ups are pulled internally to the supply shown in the power well column. All other pins are driven under the power well shown. See the "Pins With Internal Resistors", "Pins That Require External Resistors" and "Default State of Pins" sections. The 32.768 kHz input clock must not be driven high when VTR = 0V. CLOCKI32 is clock source to various logic in the part, including LED, "wake on specific key" and nFPRST debounce circuitry. The 32 KHz input clock must always be connected. There is a bit in the configuration register at 0xF0 in Logical Device A that indicates whether or not the 32KHz clock is connected. This bit determines the clock source for the logic. This bit must always be set to `0' (`0'=32 KHz clock connected; reset default=`0'). The nLPCPD pin may be tied high. The LPC interface will function properly if the nPCI_RESET signal follows the protocol defined for the nLRESET signal in the "Low Pin Count Interface Specification". However, if nLPCPD is tied high, the keyboard wakeup isolation logic will be affected. These pins (except DDC and FAN_TACH functions) are also inputs to VTR powered logic internal to the part. If DDC and FAN_TACH functions are selected on GPIOs, the pins will tri-state when VCC power is removed. External pullups must be placed on the nKBDRST and GA20M pins. If the nKBDRST and GA20M functions are to be used, the system must ensure that these pins are high. See the "That Require External Resistors" section. When DDC functions are selected on GP20-GP23, the pins become IO_SW type and require external pullups to the appropriate voltages. See the "That Require External Resistors" section. When the GPIO functions are selected, the pins are IS0D8. The IRTX2 pin is driven low upon power-up of VCC. This pin will remain low following a power-up (VCC POR) until it is selected via the IR MUX bits and serial port 2 is enabled by setting the activate bit, at which
Page 22 SMSC LPC47M172
Note 2: Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
time the pin will reflect the state of the transmit output of the Serial Port 2 block. This is a VCC powered pin. Note 10: These pins are internally pulled down to VSS only until Serial Port 2 is enabled. Once Serial Port 2 is enabled, the pull-downs are removed until VTR POR. Note 11: Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the LPC47M172. See Table 6.1 - Super I/O Block Logical Device Number and Addresses. The pin has an internal pull-down resistor that selects the non-SMSC (Intel Compatible) mode. To select this mode, the pin should be left unconnected. Connecting this pin to VTR will select the SMSC mode of the logical device numbering.
3.1
Note: PWR I IPU IPD IS IS_400 ISPU_400 ISPD_400 O8 OD8 O12 OD12 OP14 OD24 AO IO8 ISO8 ISOD8 IO12 IOP14 IOD24 IO_SW PCI_IO PCI_O PCI_I PCI_ICLK Note 1: Note 2:
Buffer Name Descriptions
Refer to the "Electrical Characteristics" section. Power and Ground Input TTL Compatible. Input with 30uA Integrated Pull-Up Input with 30uA Integrated Pull-Down Input with 250mV Schmitt Trigger. Input with 400mV Schmitt Trigger. Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Up. Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Down. Output, 8mA sink, 4mA source. Output (Open Drain), 8mA sink. Output, 12mA sink, 6mA source. Output (Open Drain), 12mA sink. Output, 14mA sink, 14mA source. Output (Open Drain), 24mA sink. Output - Analog with 5V Level Input/Output, 8mA sink, 4mA source. Input with 250mV Schmitt Trigger /Output, 8mA sink, 4mA source. Input with 250mV Schmitt Trigger, Low Leakage/Output (Open-Drain), 8mA sink. Input with Schmitt Trigger/Output, 12mA sink, 6mA source. Input/Output, 14mA sink, 14mA source. Input/Output (Open Drain), 24mA sink. Input/Output, special type. Pins of this type are connected in pairs through a switch. The switch provides a 25 ohm (max) resistance to ground when closed. Input/Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing. (Note 2) See the "PCI Local Bus Specification," Revision 2.1, Section 4.2.2. See the "PCI Local Bus Specification," Revision 2.1, Section 4.2.2 and 4.2.3.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
3.2
Pins With Internal Resistors
The following pins have internal resistors: Table 3.2 - Pins with Internal Resistors SIGNAL NAME nCPU_PRESENT nFPRST nPRIMARY_HD PWRGD_PS nSCSI nSECONDARY_HD TEST_EN RESISTOR VALUE 30uA 30uA 30uA 30uA 30uA 30uA 30uA NOTES Pull-up to VTR Pull-up to VTR Pull-up to VCC Pull-up to VTR Pull-up to VCC Pull-up to VCC Pull-down to VSS
3.3
Pins That Require External Resistors
The following pins require external resistors: Table 3.3 - Pins that Require External Resistors SIGNAL NAME SER_IRQ nLDRQ LAD[3:0] MCLK MDAT KCLK KDAT GA20M KBDRST nIO_PME nHDSEL nWGATE nWDATA nSTEP nDIR nDS0 nMTR0 DRVDEN1 DRVDEN0 nDSKCHG nRDATA nWRTPRT nTRK0 nINDEX REF5V REF5V_STBY RESISTOR VALUE 10 kohm 100 kohm 100 kohm 2.7 kohm NOTES Pull-up to VCC Pull-up to VCC Pull-up to VCC Pull-up to VREG_PS2. The VREG_PS2 is the voltage regulator for the PS/2 ports. Pull-up to VCC Pull-up to VCC Pull-up to VTR Pull-up required if used as Open-Drain Output. Pull-up to VCC.
10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 1 kohm 1 kohm 1 kohm 1 kohm 10 kohm 1 kohm 1 kohm
Page 24
Pull-up to VCC Pull-up to VCC Pull-up to VCC Pull-up to VCC Pull-up to VCC Pull-up to VCC5V Pull-up to V_5P0_STBY
SMSC LPC47M172
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
SIGNAL NAME nIDE_RSTDRV nPS_ON nBACKFEED_CUT SCK_BJT_GATE nCDC_DWN_ENAB YLW_LED nHD_LED DDCSDA_3V DDCSCL_3V DDCSDA_5V DDCSCL_5V SMB_CLK_M SMB_CLK_R SMB_DAT_M SMB_DAT_R GRN_LED GPIOs
RESISTOR VALUE 1 kohm 1 kohm 1 kohm 1 kohm 10 kohm 220 ohm 330 ohm 4.7 kohm 4.7 kohm 2.2 kohm 2.2 kohm 2.7 kohm 2.7 kohm 2.7 kohm 2.7 kohm 220 ohm design-dependant
NOTES Pull-up to VCC5V Pull-up to V_5P0_STBY Pull-up to V_5P0_STBY Pull-up to V_5P0_STBY Pull-down to VSS Pull-up to VTR Pull-up to VCC Pull-up to VCC Pull-up to VCC Pull-up to VCC5V Pull-up to VCC5V Pull-up to VCC Pull-up to VTR Pull-up to VCC Pull-up to VTR Pull-up to VTR Pull-up to appropriate voltage (not to exceed 5V)
3.4
Notes:
Default State of Pins
The following table shows the default state of pins.
Off The pin is not powered by suspend supply and is valid under main power only. Hi-Z The pin is powered, but tri-stated either because the pin is open-drain or VCC function is selected on VTR powered pin. The pin requires external pull-up when tri-stated. Active The pin is powered and active high. Running The input clock is powered and running. Input The pin is powered and driven by external circuitry to high or low level. Out The pin is powered and driven to high or low level by the part. The input or output configuration state of the pin is retained and is not affected by PCI Reset or VCC POR.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
Table 3.4 - Default State of Pins SIGNAL NAME REF5V_STBY REF5V CLOCKI CLOCKI32 nIO_PME PCI_CLK nLPCPD nPCI_RESET SER_IRQ nLDRQ nLFRAME LAD[0:3] nDSKCHG nHDSEL nRDATA nWRTPRT nTRK0 nWGATE nWDATA nSTEP nDIR nDS0 nMTR0 nINDEX DRVDEN0 DRVDEN1 nDCD1 nDSR1 RXD1 nRTS1 TXD1 nCTS1 nDTR1 (XOR) nRI1 nDCD2 PWR WELL VTR VCC VCC VTR VTR VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VTR VCC PCI RESET Active Running Running Input Input Input Input Input Input Input Input Out - low Input Input Input Hi-Z Hi-Z Out - low Out - low Hi-Z Hi-Z Input Out - high Out - high Input Input Input Out - high Out - low Input Out - high Input Active Running Running Input Input Input Input Input Input Input Input Out - low Input Input Input Hi-Z Hi-Z Out - low Out - low Hi-Z Hi-Z Input Out - high Out - high Input Input Input Out - high Out - low Input Out - high Input VCC POR VTR POR Active Off Off Running Hi-Z Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Input Off This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. NOTES This pin requires external pullup to V_5P0_STBY This pin requires external pullup to VCC5V
nDSR2
VCC
Input
Input
Off
RXD2 nRTS2 TXD2
VCC VCC VCC
Input Out - high Out - low
Input Out - high Out - low
Page 26
Off Off Off
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
SIGNAL NAME nCTS2 nDTR2 nRI2
PWR WELL VCC VCC VTR
PCI RESET Input Out - high -
VCC POR Input Out - high -
VTR POR Off Off Input
NOTES This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled.
IRRX2 IRTX2 SLCT PE BUSY nACK PD[7:0] ERROR nSLCTIN nINITP nALF nSTROBE MCLK MDAT KCLK KDAT GA20M nKBDRST nAUD_LINK_RST nCDC_DWN_ENAB/ GP24 nCDC_DWN_RST nFPRST nBACKFEED_CUT LATCHED_BF_CUT SCK_BJT_GATE nSCSI GRN_LED YLW_LED nHD_LED nSECONDARY_HD nPRIMARY_HD nIDE_RSTDRV PWRGD_PS nPS_ON nCPU_PRESENT
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VTR VTR VTR VTR VTR VTR VTR VCC VTR VTR VCC VCC VCC VCC VTR VTR VTR
Input Out - low Input Input Input Input Input Input Out - High Out - High Out - High Out - High Hi-Z Hi-Z Hi-Z Hi-Z Input Hi-Z Input Input Out - low -
Input Out - low Input Input Input Input Input Input Out - High Out - High Out - High Out - High Hi-Z Hi-Z Hi-Z Hi-Z Input Hi-Z Input Input Out - low -
Off Off Off Off Off Off Off Off Off Off Off Off Off Input Off Input Off Off Input Input Out - low Input Hi-Z Out - low Hi-Z Off Out - low Out - low Off Off Off Off Input Hi-Z Input
This pin is pulled up internally This pin requires external pullup to V_5P0_STBY. This pin requires external pullup to V_5P0_STBY. This pin is pulled up internally
This pin is pulled up internally This pin is pulled up internally Requires external pull-up to VCC5V Requires external pull-up to V_5P0_STBY This pin is pulled up internally
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
SIGNAL NAME nSLP_S3 nSLP_S5 nRSMRST PWRGD_3V nPCIRST_OUT nPCIRST_OUT2 GP10-GP15 GP16 FAN_TACH1 GP17 FAN_TACH2 SMB_CLK_M SMB_CLK_R SMB_DAT_M SMB_DAT_R DDCSDA_5V
PWR WELL VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR
PCI RESET Out - low Out - low Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
VCC POR Out - low Out - low Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z -
VTR POR Input Input Out - low Out - low Out - low Out - low Input Input Hi-Z Input Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
NOTES
The GPIO and FAN_TACH functions are multiplexed on the same pin with GPIO as the default function.
GP20 DDCSCL_5V VTR GP21 DDCSDA_3V VTR GP22 DDCSCL_3V VTR GP23
Hi-Z Hi-Z -
The DDC and GPIO functions are multiplexed on the same pin with DDC as the default function. DDC function requires external pull-up to VCC5V.
The DDC and GPIO functions are multiplexed on the same pin with DDC as the default function. DDC function requires external pull-up to VCC. Test Mode pin. This pin has internally pull-down to VSS. External pull-up required to enable the test mode.
TEST_EN
VTR
-
-
Input
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
Chapter 4
Block Diagram
FAN_TACH1*
FAN_TACH2*
CLOCKI32
GRN_LED
YLW_LED
TEST_EN
CLOCKI
SER_IRQ PCI_CLK LAD[3:0] nLFRAME nLDRQ nPCI_RESET nLPCPD nIO_PME GP10-GP15, GP16*, GP17* (GP20-GP23)* GP24* F_CAP V_5P0_STBY nRSMRST REF5V REF5V_STBY nAUD_LINK_RST nCDC_DWN_ENAB* nCDC_DWN_RST nPCI_RST_OUT nPCI_RST_OUT2 nIDE_RSTDRV nPRIMARY_HD nSECONDARY_HD nSCSI nHD_LED nFPRST nBACKFEED_CUT LATCHED_BF_CUT SCK_BJT_GATE nPS_ON PWRGD_PS
nSLP_S5
SERIAL IRQ / Interrupt Generating Registers
CLOCK GEN
Power LED
FAN Monitoring
XOR-Chain
XOR*
PD[7:0] Multi-Mode Parallel Port with ChiProtectTM BUSY, SLCT, PE, nERROR, nACK nSTROBE, nINITP, nSLCTIN, nALF RXD TXD nCTS nRTS nDSR nDTR* nDCD nRI RXD2 TXD2 nCTS2 nRTS2 nDSR2 nDTR2 nDCD2 nRI2 IRRX2 IRTX2 KDAT, MDAT
LPC Bus Interface
Internal Bus (Data, Address, and Control lines) PME / Power Control
GPIOs
LPC47M172 (128 QFP)
VCC (3.3V) VTR (3.3V)
High-Speed 16550A UART PORT
Resume Reset Generation 5V Reference Generation CNR Logic
V_5P0_STBY High-Speed 16550A UART PORT 2 W/ Infrared Configuration Registers nPCI_RESET
Buffered PCI Reset
Keyboard/Mouse 8042 Controller
KCLK, MCLK GA20M nKBDRST
Hard Drive Front Panel LED SMSC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE
WDATA WCLOCK RCLOCK RDATA DIGITAL DATA SEPARATOR WITH WRITE PRECOMPENSATION
Power Sequencing
SMBus Isolation
VGA Voltage Translation
SMB_DAT_M
SMB_CLK_R
SMB_DAT_R
DDCSDA_5V*
DDCSDA_3V*
DDCSCL_5V*
nCPU_PRESENT
DDCSCL_3V*
SMB_CLK_M
nDIR, nSTEP, nDS0, nMTR0
DRVDEN0, DRVDEN1
nWGATE, nHDSEL
nTRK0, nDSKCHG, nINDEX, nWRTPRT
nSLP_S3
PWRGD_3V
nSLP_S5
nWDATA
nRDATA
Note 1: This diagram shows the various functions available on the chip (not pin layout). The block diagram should not be used for pin count. Note 2: Functions with asterisks (*) are located on multifunctional pins.
Figure 4.1 - LPC47M172 Block Diagram
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
Chapter 5
Power and Clock Functionality
The LPC47M172 has three power planes: VCC, VTR and V5P0_STBY.
5.1
3 Volt Operation / 5 Volt Tolerance
The LPC47M172 is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the operating input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected (they do not impose a load on any external VCC powered circuitry). The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. The nRSMRST pin is also 3.3V only. The following lists the pins that are 3.3V only (not 5V tolerant): LAD[3:0] nLFRAME nLDRQ nLPCPD nRSMRST The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins: nPCI_RESET PCI_CLK SER_IRQ nIO_PME
5.2
VCC Power
The LPC47M172 is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). Description" Section and the "Maximum Current Values" subsection. See the "Operational
5.3
VTR Power
The LPC47M172 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface and other suspend state logic when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle Power Functionality subsection and Maximum Current Values subsection. If the LPC47M172 is not intended to provide wake-up and/or suspend power capabilities on standby current, VTR can be connected to VCC. The VTR pin generates a VTR Power-on-Reset signal to initialize these components.
Note:
If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum potential at least 10 s before VCC begins a power-on cycle. When VTR and VCC are fully powered, the potential difference between the two supplies must not exceed 500mV.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
5.3.1
Trickle Power Functionality
When the LPC47M172 is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The following lists the wakeup events: UART1 and UART 2 Ring Indicator Keyboard data Mouse data "Wake on Specific Key" Logic GPIOs for wakeup. See below. The following requirements apply to all I/O pins that are specified to be 5 volt tolerant. I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR. I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present. The GPIOs that are used for PME wakeup as input are GP10-GP17 and GP20-GP23 Buffers are powered by VTR. These pins have input buffers into the wakeup logic that are powered by VTR. GP24 does not have input buffer into the wakeup logic. The output buffer of GP24 is by VTR but does this pin does not have an input buffer into wakeup logic powered by VTR. For blocks, registers and pins that are powered by VTR see Table 3.1 and Figure 4.1.
5.4
V5P0_STBY Power
The V5P0_STBY pin is used in nRSMRST generation circuit. The V5P0_STBY, however, does not power the nRSMRST pad.
5.5
32.768 kHz Trickle Clock Input
The LPC47M172 utilizes a 32.768 kHz trickle input to supply a clock signal for the nFPRST debounce circuitry, LED blink and wake on specific key function.
5.5.1
Indication of 32KHZ Clock
There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M172. This bit is located at bit 0 of the CLOCKI32 configuration register at 0xF0 in Logical Device A (see Table 11.14). This register is powered by VTR and reset on a VTR POR. Bit[0] (CLK32_PRSN) is defined as follows: 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded).
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
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Bit 0 controls the source of the 32kHz (nominal) clock for the nFPRST debounce circuitry, the LED blink logic and the "wake on specific key" logic. When the external 32kHz clock is connected, that will be the source for the nFPRST debounce circuitry, LED and "wake on specific key" logic. When the external 32kHz clock is not connected, an internal 32kHz clock source will be derived from the 14MHz clock for the "wake on specific key" logic. The nFPRST debounce circuitry and LED require the 32kHz clock be always connected. The "wake on specific key" function will not work under VTR power (VCC removed) if the external 32kHz clock is not connected. It will work under VCC power even if the external 32 kHz clock is not connected.
5.6
14.318 MHz Clock Input
The LPC47M172 utilizes a 14.318 MHz clock input (CLOCKI). This clock is used to generate specific clocks needed for various logic (including SIO functions, Fan Tachometer, etc.) in the LPC47M172. The CLOCKI is powered by VCC and is not available in VTR power only (VCC=0).
5.7
Internal PWRGOOD
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as VCC cycles on and off. When the internal PWRGOOD signal is "1" (active), VCC > 2.3V (nominal), and the LPC47M172 host interface is active. When the internal PWRGOOD signal is "0" (inactive), VCC <= 2.3V (nominal), and the LPC47M172 host interface is inactive; that is, LPC bus reads and writes will not be decoded. The LPC47M172 device pins nIO_PME, CLOCKI32, KDAT, MDAT, nRI1, nRI2, and most GPIOs (as input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. Other VTR powered pins listed in Table 3.1 also remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. See Trickle Power Functionality section.
5.8
Maximum Current Values
See the "Operational Description" section for the maximum current values. The maximum VTR current, ITR, is given with all outputs open (not loaded), and all inputs transitioning from/to 0V to/from 3.3V. The total maximum current for the part is the unloaded value PLUS the maximum current sourced by the pin that is driven by VTR. The pins that are powered by VTR are listed in the Table 3.1. The push-pull capable outputs will source minimum current specified in Table 12.2 at 2.4V when driving. The maximum VCC current, ICC, is given with all outputs open (not loaded) and all inputs transitioning from/to 0V to/from 3.3V.
5.9
Power Management Events (PME/SCI)
The LPC47M172 offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal. See the "PME Support" section.
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Chapter 6
Functional Description
The following sections describe the functional blocks located in the LPC47M172 (see Figure 4.1). The various Super I/O components are described in the following sections and their registers are implemented as typical Plug-and-Play components (see section Chapter 11 - Configuration on page 173).
6.1
Super I/O Registers
Table 6.1 shows the logical device number and addresses of FDC, Serial and Parallel ports, Keyboard/Mouse, Power Control and GPIO Block, Runtime register block and configuration register block of the Super I/O immediately after power up. The logical device numbering is controlled by the LD_NUM bit in the TEST 7 configuration register (0x29). The state of LD_NUM is determined by pin 117 as described in Chapter 2. The base addresses of the blocks can be programmed via the configuration registers. Some addresses are used to access more than one register. Refer to the "Configuration" section for configuration register description.
Table 6.1 - Super I/O Block Logical Device Number and Addresses LD_NUM bit = 0 (default) (Non-Standard SMSC Register Sets) LD NUMBER 00h 01h DEVICE NAME Floppy Disk Controller Parallel Port BLOCK ADDRESS Base+(0-5) and +(7) Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) Base+(0-7) Base+(0-7) LD_NUM bit = 1 (Standard SMSC Register Sets) LD DEVICE BLOCK ADDRESS NUMBER NAME 00h 01h Floppy Disk Controller Base+(0-5) and +(7) -
02h 03h
Serial Port 2 Serial Port 1
02h 03h
Serial Port 2 Parallel Port
04h 05h 06h 07h 08h 09h 0Ah
Power Control Mouse Keyboard GPIO -
Base+(0-31) 60, 64 Base+(0-31) -
04h 05h 06h 07h 08h 09h 0Ah
-
Configuration
Base + (0-1)
-
Serial Port 1 Keyboard/ Mouse Runtime Register Block - contains Power Control and GPIO Block registers in this mode. Configuration
Base+(0-7) Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) Base+(0-7) 60, 64 Base+(0-63)
Base + (0-1)
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6.2
Host Processor Interface (LPC)
The host processor communicates with the LPC47M172 through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table 6.1. Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.
6.3
LPC Interface
The following sub-sections specify the implementation of the LPC bus.
6.3.1
LPC Interface Signal Definition
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal characteristics.
SIGNAL NAME LAD[3:0] nLFRAME nPCI_RESET nLDRQ nIO_PME nLPCPD SER_IRQ PCI_CLK Note:
TYPE I/O Input Input Output OD Input I/O Input
DESCRIPTION LPC address/data bus. Multiplexed command, address and data bus. Frame signal. Indicates start of new cycle and termination of broken cycle PCI Reset. Used as LPC Interface Reset. Encoded DMA/Bus Master request for the LPC interface. Power Mgt Event signal. Allows the LPC47M172 to request wakeup. Powerdown Signal. Indicates that the LPC47M172 should prepare for power to be shut on the LPC interface. Serial IRQ. PCI Clock.
The CLKRUN# signal is not implemented in this part.
6.3.2
LPC Cycles
The following cycle types are supported by the LPC protocol. CYCLE TYPE I/O Write I/O Read DMA Write DMA Read 1 Byte 1 Byte 1 Byte 1 Byte TRANSFER SIZE
LPC47M172 ignores cycles that it does not support.
6.3.3
Field Definitions
The data transfers are based on specific fields that are used in various combinations, depending on the cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the LPC bus between the host and the LPC47M172. See the Low Pin Count (LPC) Interface Specification Revision 1.0 from Intel, Section 4.2 for definition of these fields.
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6.3.4
NLFRAME Usage
nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal is to be used by the LPC47M172 to know when to monitor the bus for a cycle. This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the LPC47M172 monitors the bus to determine whether the cycle is intended for it. The use of nLFRAME allows the LPC47M172 to enter a lower power state internally. There is no need for the LPC47M172 to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks. When the LPC47M172 samples nLFRAME active, it immediately stops driving the LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information. The nLFRAME signal functions as described in the Low Pin Count (LPC) Interface Specification, Revision 1.0.
6.3.5
I/O Read and Write Cycles
The LPC47M172 is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times. Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it up into 8-bit transfers. See the "Low Pin Count (LPC) Interface Specification" Reference, Section 5.2, for the sequence of cycles for the I/O Read and Write cycles.
6.3.6
DMA Read and Write Cycles
DMA read cycles involve the transfer of data from the host (main memory) to the LPC47M172. DMA write cycles involve the transfer of data from the LPC47M172 to the host (main memory). Data will be coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47M172 are 1, 2 or 4 bytes. See the "Low Pin Count (LPC) Interface Specification" Reference, Section 6.4, for the field definitions and the sequence of the DMA Read and Write cycles.
6.3.7
DMA Protocol
DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47M172 and special encodings on LAD[3:0] from the host. The DMA mechanism for the LPC bus is described in the "Low Pin Count (LPC) Interface Specification," Revision 1.0.
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6.3.8
Power Management
CLOCKRUN Protocol The CLKRUN# pin is not implemented in the LPC47M172. See the "Low Pin Count (LPC) Interface Specification" Revision 1.0, Section 8.1. LPCPD Protocol See the "Low Pin Count (LPC) Interface Specification" Revision 1.0, Section 8.2.
6.3.9
SYNC Protocol
See the "Low Pin Count (LPC) Interface Specification" Revision 1.0, Section 4.2.1.8 for a table of valid SYNC values. Typical Usage The SYNC pattern is used to add wait states. For read cycles, the LPC47M172 immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47M172 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The LPC47M172 will choose to assert 0101 or 0110, but not switch between the two patterns. The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The LPC47M172 uses a SYNC of 0101 for all wait states in a DMA transfer. The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47M172 uses a SYNC of 0110 for all wait states in an I/O transfer. The SYNC value is driven within 3 clocks. SYNC Timeout The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it will abort the cycle. The LPC47M172 does not assume any particular timeout. When the host is driving SYNC, it may have to insert a very large number of wait states, depending on PCI latencies and retries. SYNC Patterns and Maximum Number of SYNCS If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8. If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47M172 has protection mechanisms to complete the cycle. This is used for EPP data transfers and should utilize the same timeout protection that is in EPP.
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SYNC Error Indication The LPC47M172 reports errors via the LAD[3:0] = 1010 SYNC encoding. If the host was reading data from the LPC47M172, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47M172. If the host was writing data to the LPC47M172, the data had already been transferred. In the case of multiple byte cycles, such as memory and DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not be transferred.
6.3.10 I/O and DMA START Fields
I/O and DMA cycles use a START field of 0000. Reset Policy The following rules govern the reset policy: When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus. When nPCI_RESET goes active (low): the host drives the nLFRAME signal high, tristates the LAD[3:0] signals, and ignores the nLDRQ signal. the LPC47M172 ignores nLFRAME, tristate the LAD[3:0] pins and drive the nLDRQ signal inactive (high).
6.3.11 LPC Transfers
Wait State Requirements I/O Transfers The LPC47M172 inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would normally be deasserted in an ISA transfer (i.e., EPP or IrCC transfers) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us). DMA Transfers The LPC47M172 inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of 0101 is used for all DMA transfers. See the example timing for the LPC cycles in the "Timing Diagrams" section.
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6.4
Floppy Disk Controller
The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.
6.4.1
FDC Configuration Registers
The FDC configuration registers are summarized Table 11.2 in the "Configuration" section. The FDC logical device configuration registers (0xF0, 0xF1, 0xF2 and 0xF4) are defined in Table 11.9.
6.4.2
FDC Internal Registers
The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 6.2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. Table 6.2 - Status, Data and Control Registers (Shown with base addresses of 3F0 and 370) PRIMARY ADDRESS 3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7 SECONDARY ADDRESS 370 371 372 373 374 374 375 376 377 377 R/W R R R/W R/W R W R/W R W REGISTER Status Register A (SRA) Status Register B (SRB) Digital Output Register (DOR) Tape Drive Register (TDR) Main Status Register (MSR) Data Rate Select Register (DSR) Data (FIFO) Reserved Digital Input Register (DIR) Configuration Control Register (CCR)
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6.4.3
Status Register A (SRA)
Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0.
PS/2 Mode 7 INT PENDIN G 0 6 nDRV2 5 STEP 4 nTRK0 3 HDSEL 2 nINDX 1 nWP 0 DIR
RESET COND.
1
0
N/A
0
N/A
N/A
0
BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 This function is not supported. This bit is always read as "1". BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. PS/2 Model 30 Mode 7 INT PENDING RESET COND. BIT 0 DIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction.
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6 DRQ 0
0
5 STEP F/F 0
4 3 2 TRK0 nHDSEL INDEX N/A 1 N/A
1 WP N/A
0 nDIR 1
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BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 HEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. BIT 6 DMA REQUEST Active high status of the DMA request pending. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt.
6.4.4
Status Register B (SRB)
Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1.
PS/2 Mode 7 1 RESET COND. BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. 1 6 1 1 5 DRIVE SEL0 0 4 3 2 WDATA RDATA WGATE TOGGLE TOGGLE 0 0 0 1 MOT EN1 0 0 MOT EN0 0
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BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1" PS/2 Model 30 Mode 7 nDRV2 RESET COND. BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1
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6.4.5
Digital Output Register (DOR)
Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 DMAEN 0 2 nRESET 0 1 DRIVE SEL1 0 0 DRIVE SEL0 0
RESET COND.
BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and interrupt functions. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic "0". BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. DRIVE 0 1 DOR VALUE 1CH 2DH
Table 6.3 - Internal 2 Drive Decode - Normal DIGITAL OUTPUT REGISTER Bit 5 X 1 0 Bit 4 1 X 0 Bit1 0 0 X Bit 0 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 1 0 1 nDS0 0 1 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4
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Table 6.4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped DIGITAL OUTPUT REGISTER Bit 5 X 1 0 Bit 4 1 X 0 Bit1 0 0 X Bit 0 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 0 1 1 nDS0 1 0 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5
BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the LPC47M172. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the LPC47M172.
6.4.6
Tape Drive Register (TDR)
Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 6.5 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. Table 6.5 - Tape Select Bits TAPE SEL1 (TDR.1) 0 0 1 1 TAPE SEL0 (TDR.0) 0 1 0 1 DRIVE SELECTED None 1 2 3
Normal Floppy Mode Normal mode.Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are `0'. REG 3F3 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 tape sel1 DB0 tape sel0
Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 REG 3F3 Reserved Reserved DB5 DB4 Drive Type ID DB3 DB2 Floppy Boot Drive DB1 tape sel1 DB0 tape sel0
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Table 6.6 - Drive Type ID DIGITAL OUTPUT REGISTER Bit 1 Bit 0 0 0 0 1 1 0 1 1 Note: REGISTER 3F3 - DRIVE TYPE ID Bit 5 Bit 4 L0-CRF2 - B1 L0-CRF2 - B0 L0-CRF2 - B3 L0-CRF2 - B2 L0-CRF2 - B5 L0-CRF2 - B4 L0-CRF2 - B7 L0-CRF2 - B6
L0-CRF2-Bx = FDC Logical Device, Configuration Register F2, Bit x.
6.4.7
Data Rate Select Register (DSR)
Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30. 7 6 S/W POWER RESET DOWN 0 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PREDRATE DRATE COMP0 SEL1 SEL0 0 1 0
RESET COND.
This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 6.7 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. This starting track number can be changed by the configure command.
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Table 6.7 - Precompensation Delays PRECOMP 432 111 001 010 011 100 101 110 000 BIT 5 UNDEFINED Should be written as a logic "0". BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Separator circuits will be turned off. The controller will come out of manual low power. Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x19 in the Power Control/Runtime Register block. Table 6.8 - Data Rates DRIVE RATE DRT1 0 0 0 0 0 0 0 0 1 1 1 1 DRT0 0 0 0 0 1 1 1 1 0 0 0 0 DATA RATE SEL1 1 0 0 1 1 0 0 1 1 0 0 1 SEL0 1 0 1 0 1 0 1 0 1 0 1 0 DATA RATE MFM 1Meg 500 300 250 1Meg 500 500 250 1Meg 500 2Meg 250 FM --250 150 125 --250 250 125 --250 --125 DENSEL 1 1 0 0 1 1 0 0 1 1 0 0 DRATE(1) 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 PRECOMPENSATION DELAY (NSEC) <2Mbps 2Mbps 0 0.00 20.8 41.67 41.7 83.34 62.5 125.00 83.3 166.67 104.2 208.33 125 250.00 Default Default Default: See Table 6.10
Note 1:
00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive 10 = 2 Meg Tape The DRATE and DENSEL values are mapped onto the DRVDEN pins.
Drive Rate Table (Recommended)
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Table 6.9 - DRVDEN Mapping DT1 0 DT0 0 DRVDEN1 (1) DRATE0 DRVDEN0 (1) DENSEL DRIVE TYPE 4/2/1 MB 3.5" 2/1 MB 5.25" FDDS 2/1.6/1 MB 3.5" (3-MODE) PS/2
1 0 1
0 1 1
DRATE0 DRATE0 DRATE1
DRATE1 nDENSEL DRATE0
Table 6.10 - Default Precompensation Delays DATA RATE 2 Mbps 1 Mbps 500 Kbps 300 Kbps 250 Kbps PRECOMPENSATION DELAYS 20.8 ns 41.67 ns 125 ns 125 ns 125 ns
6.4.8
Main Status Register
Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer. 7 RQM 6 DIO 5 NON DMA 4 CMD BUSY 3 2 1 DRV1 BUSY 0 DRV0 BUSY
Reserved Reserved
BIT 0 - 1 DRV x BUSY These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. BIT 4 COMMAND BUSY This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte. BIT 5 NON-DMA Reserved, read `0'. This part does not support non-DMA mode. BIT 6 DIO Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required. BIT 7 RQM Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.
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6.4.9
Data Register (FIFO)
Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 6.11 gives several examples of the delays with a FIFO. The data is based upon the following formula: Threshold # x 1 DATA RATE x 8 - 1.5 us = DELAY
At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred. An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. Table 6.11 - FIFO Service Delay FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes MAXIMUM DELAY TO SERVICING AT 2 MBPS DATA RATE 1 x 4 us - 1.5 us = 2.5 us 2 x 4 us - 1.5 us = 6.5 us 8 x 4 us - 1.5 us = 30.5 us 15 x 4 us - 1.5 us = 58.5 us MAXIMUM DELAY TO SERVICING AT 1 MBPS DATA RATE 1 x 8 us - 1.5 us = 6.5 us 2 x 8 us - 1.5 us = 14.5 us 8 x 8 us - 1.5 us = 62.5 us 15 x 8 us - 1.5 us = 118.5 us MAXIMUM DELAY TO SERVICING AT 500 KBPS DATA RATE 1 x 16 us - 1.5 us = 14.5 us 2 x 16 us - 1.5 us = 30.5 us 8 x 16 us - 1.5 us = 126.5 us 15 x 16 us - 1.5 us = 238.5 us
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6.4.10 Digital Input Register (DIR)
Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG N/A 6 0 N/A 5 0 N/A 4 0 N/A 3 0 N/A 2 0 N/A 1 0 N/A 0 0 N/A
RESET COND. BIT 0 - 6 UNDEFINED
The data bus outputs D0 - 6 are read as `0'. BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime register at offset 0x18). PS/2 Mode 7 DSK CHG N/A 6 1 N/A 5 1 N/A 4 1 N/A 3 1 N/A 2 DRATE SEL1 N/A 1 DRATE SEL0 N/A 0 nHIGH DENS 1
RESET COND. BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. BITS 1 - 2 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BITS 3 - 6 UNDEFINED Always read as a logic "1" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime register at offset 0x18). Model 30 Mode 7 DSK CHG RESET COND. N/A 6 0 0 5 0 0 4 0 0 3 2 1 DMAEN NOPREC DRATE SEL1 0 0 1 0 DRATE SEL0 0
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BITS 0 - 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 NOPREC This bit reflects the value of NOPREC bit set in the CCR register. BIT 3 DMAEN This bit reflects the value of DMAEN bit set in the DOR register bit 3. BITS 4 - 6 UNDEFINED Always read as a logic "0" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime register at offset 0x18).
6.4.11 Configuration Control Register (CCR)
Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 0 RESET COND. N/A 6 0 N/A 5 0 N/A 4 0 N/A 3 0 N/A 2 0 N/A 1 DRATE SEL1 1 0 DRATE SEL0 0
BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values. BIT 2 - 7 RESERVED Should be set to a logical "0" PS/2 Model 30 Mode 7 0 RESET COND. N/A 6 0 N/A 5 0 N/A 4 0 N/A 3 0 N/A 2 1 NOPREC DRATE SEL1 N/A 1 0 DRATE SEL0 0
BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values. BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset.
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BIT 3 - 7 RESERVED Should be set to a logical "0" Table 6.9 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets.
6.4.12 Status Register Encoding
During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. Table 6.12 - Status Register 0 BIT NO. 7,6 SYMBOL IC NAME Interrupt Code DESCRIPTION 00 - Normal termination of command. The specified command was properly executed and completed without error. 01 - Abnormal termination of command. Command execution was started, but was not successfully completed. 10 - Invalid command. The requested command could not be executed. 11 - Abnormal termination caused by Polling. The FDC completed a Seek, Relative Seek or Recalibrate command (used during a Sense Interrupt Command). The TRK0 pin failed to become a "1" after: 1. Step pulses in the Recalibrate command. 2. The Relative Seek command caused the FDC to step outward beyond Track 0. Unused. This bit is always "0". The current head address. The current selected drive.
5
SE
Seek End
4
EC
Equipment Check
3 2 1,0
H DS1,0
Head Address Drive Select
Table 6.13 - Status Register 1 BIT NO. 7 SYMBOL EN NAME End of Cylinder DESCRIPTION The FDC tried to access a sector beyond the final sector of the track (255D). Will be set if TC is not issued after Read or Write Data command. Unused. This bit is always "0". The FDC detected a CRC error in either the ID field or the data field of a sector. Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in data overrun or underrun. Unused. This bit is always "0".
6 5 4
DE OR
Data Error Overrun/ Underrun
3
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BIT NO. 2
SYMBOL ND
1
NW
0
MA
DESCRIPTION Any one of the following: 1. Read Data, Read Deleted Data command - the FDC did not find the specified sector. 2. Read ID command - the FDC cannot read the ID field without an error. 3. Read A Track command - the FDC cannot find the proper sector sequence. Not Writeable WP pin became a "1" while the FDC is executing a Write Data, Write Deleted Data, or Format A Track command. Any one of the following: Missing Address Mark 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the nINDEX pin twice. 2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track.
NAME No Data
Table 6.14 - Status Register 2 BIT NO. 7 6 SYMBOL CM NAME Control Mark DESCRIPTION Unused. This bit is always "0". Any one of the following: Read Data command - the FDC encountered a deleted data address mark. Read Deleted Data command - the FDC encountered a data address mark. The FDC detected a CRC error in the data field.
5 4 3 2 1
DD WC
BC
0
MD
The track address from the sector ID field is different from the track address maintained inside the FDC. Unused. This bit is always "0". Unused. This bit is always "0". Bad Cylinder The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. Missing Data The FDC cannot detect a data address mark or a Address Mark deleted data address mark.
Data Error in Data Field Wrong Cylinder
Table 6.15 - Status Register 3 BIT NO. 7 6 5 4 3 2 1,0 SYMBOL WP NAME Write Protected Track 0 DESCRIPTION Unused. This bit is always "0". Indicates the status of the WRTPRT pin.
T0 HD DS1,0
Unused. This bit is always "1". Indicates the status of the TRK0 pin. Unused. This bit is always "1". Head Address Indicates the status of the HDSEL pin. Drive Select Indicates the status of the DS1, DS0 pins.
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RESET There are three sources of system reset on the FDC: the nPCI_RESET pin, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state. All operations are terminated upon a nPCI_RESET, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC. On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command. nPCI_RESET Pin (Hardware Reset) The nPCI_RESET pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state. DOR Reset vs. DSR Reset (Software Reset) These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state.
6.5
Modes of Operation
The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the state of the Interface Mode bits in FDC logical device -CRF0[3,2].
6.5.1
PC/AT Mode
The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is an active high signal.
6.5.2
PS/2 Mode
This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care". The DMA and interrupt functions are always enabled, and DENSEL is active low.
6.5.3
Model 30 Mode
This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is active low.
6.6
DMA Transfers
DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a DMA request cycle. DMA read, write and verify cycles are supported. The FDC supports two DMA transfer modes: Single Transfer and Burst Transfer. Burst mode is enabled via FDC Logical Device -CRF0-Bit[1].
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6.7
Controller Phases
For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections.
6.7.1
Command Phase
After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Please refer to section 6.10 Command Set/Descriptions). These bytes of data must be transferred in the order prescribed. Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next phase as defined by the command definition. The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" condition.
6.7.2
Execution Phase
All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is transferred by a read/write or DMA cycle depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, is defined as the number of bytes available to the FDC when service is requested from the host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. Non-DMA Mode - Transfers from the FIFO to the Host This part does not support non-DMA mode. Non-DMA Mode - Transfers from the Host to the FIFO This part does not support non-DMA mode.
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DMA Mode - Transfers from the FIFO to the Host The FDC generates a DMA request cycle when the FIFO contains (16 - ) bytes, or the last byte of a full sector transfer has been placed in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The FDC will deactivate the DMA request when the FIFO becomes empty by generating the proper sync for the data transfer. DMA Mode - Transfers from the Host to the FIFO. The FDC generates a DMA request cycle when entering the execution phase of the data transfer commands. The DMA controller must respond by placing data in the FIFO. The DMA request remains active until the FIFO becomes full. The DMA request cycle is reasserted when the FIFO has bytes remaining in the FIFO. The FDC will terminate the DMA cycle after a TC, indicating that no more data is required.
6.8
Data Transfer Termination
The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun and end-of-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer. If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector as if a TC cycle was received. The only difference between these implicit functions and TC cycle is that they return "abnormal termination" result status. Such status indications can be ignored if they were expected. Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay.
6.9
Result Phase
The generation of the interrupt determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start. RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command.
6.10
Command Set/Descriptions
Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer to Table 6.16 for explanations of the various symbols used. Table 6.17 lists the required parameters and the results associated with each command that the FDC is capable of performing.
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Table 6.16 - Description of Command Symbols SYMBOL C D D0, D1 NAME Cylinder Address Data Pattern Drive Select 0-1 DESCRIPTION The currently selected address; 0 to 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular drives on the Perpendicular Mode Command. A "1" indicates a perpendicular drive. If this bit is 0, then the head will step out from the spindle during a relative seek. If set to a 1, the head will step in toward the spindle. DS1 DS0 DRIVE 0 0 Drive 0 0 1 Drive 1 By setting N to zero (00), DTL may be used to control the number of bytes transferred in disk read/write commands. The sector size (N = 0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX. When this bit is "1" the "DTL" parameter of the Verify command becomes SC (number of sectors per track). This active low bit when a 0, enables the FIFO. A "1" disables the FIFO (default). When set, a seek operation will be performed before executing any read or write command that requires the C parameter in the command phase. A "0" disables the implied seek. The final sector number of the current track. Alters Gap 2 length when using Perpendicular Mode. The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field. The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command for actual delays. Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a "software Reset". (A reset caused by writing to the appropriate bits of either the DSR or DOR) A one selects the double density (MFM) mode. A zero selects single density (FM) mode. When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0.
DIR DS0, DS1
Direction Control Disk Drive Select
DTL
Special Sector Size
EC EFIFO EIS
Enable Count Enable FIFO Enable Implied Seek End of Track Gap Length Head Address Head Load Time
EOT GAP GPL H/HDS HLT
HUT
Head Unload Time
LOCK
MFM MT
MFM/FM Mode Selector Multi-Track Selector
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SYMBOL N
NCN ND OW PCN POLL PRETRK
R
RCN SC
SK
SRT
ST0 ST1 ST2 ST3 WGATE
NAME DESCRIPTION Sector Size Code This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive. N SECTOR SIZE 00 128 Bytes 01 256 Bytes 02 512 Bytes 03 1024 Bytes ... ... 07 16K Bytes The desired cylinder number. New Cylinder Number Non-DMA Mode Write `0'. This part does not support non-DMA mode. Flag Overwrite The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to 1. OW id defined in the Lock command. Present Cylinder The current position of the head at the completion of Sense Number Interrupt Status command. Polling Disable When set, the internal polling routine is disabled. When clear, polling is enabled. Precompensation Programmable from track 00 to FFH. Start Track Number Sector Address The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. Relative Cylinder Relative cylinder offset from present cylinder as used by the Number Relative Seek command. Number of The number of sectors per track to be initialized by the Format Sectors Per Track command. The number of sectors per track to be verified during a Verify command when EC is set. Skip Flag When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to "0", the sector is read or written the same as the read and write commands. Step Rate Interval The time interval between step pulses issued by the FDC. Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to the SPECIFY command for actual delays. Status 0 Registers within the FDC which store status information after a command has been executed. This status information is available Status 1 to the host during the result phase after command execution. Status 2 Status 3 Write Gate Alters timing of WE to allow for pre-erase loads in perpendicular drives.
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6.10.1 Instruction Set
Table 6.17 - Instruction Set READ DATA DATA BUS D5 D4 D3 D2 D1 D0 REMARKS SK 0 0 1 1 0 Command Codes 0 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N READ DELETED DATA DATA BUS D5 D4 D3 D2 D1 D0 REMARKS SK 0 1 1 0 0 Command Codes 0 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N
PHASE Command
R/W W W W W W W W W W
D7 MT 0
D6 MFM 0
Execution Result R R R R R R R
PHASE Command
R/W W W W W W W W W W
D7 MT 0
D6 MFM 0
Execution Result R R R R R R R
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PHASE Command
R/W W W W W W W W W W
D7 MT 0
D6 MFM 0
Execution Result R R R R R R R
WRITE DATA DATA BUS D5 D4 D3 D2 D1 D0 REMARKS 0 0 0 1 0 1 Command Codes 0 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N WRITE DELETED DATA DATA BUS D5 D4 D3 D2 D1 0 0 1 0 0 0 0 0 HDS DS1 C H R N EOT GPL DTL ST0 ST1 ST2 C H R N Data transfer between the FDD and system. Status information after Command execution. Sector ID information after Command execution.
PHASE Command
R/W W W W W W W W W W
D7 MT 0
D6 MFM 0
D0 1 DS0
REMARKS Command Codes Sector ID information prior to Command execution.
Execution Result R R R R R R R
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PHASE Command
R/W W W W W W W W W W
D7 0 0
D6 MFM 0
D5 0 0
READ A TRACK DATA BUS D4 D3 D2 D1 0 0 0 1 0 0 HDS DS1 C H R N EOT GPL DTL
D0 0 DS0
REMARKS Command Codes Sector ID information prior to Command execution.
Execution
Result
R R R R R R R
ST0 ST1 ST2 C H R N VERIFY DATA BUS D4 D3 D2 1 0 1 0 0 HDS C H R N EOT GPL DTL/SC ST0 ST1 ST2 C H R N
Data transfer between the FDD and system. FDC reads all of cylinders' contents from index hole to EOT. Status information after Command execution. Sector ID information after Command execution.
PHASE Command
R/W W W W W W W W W W
D7 MT EC
D6 MFM 0
D5 SK 0
D1 1 DS1
D0 0 DS0
REMARKS Command Codes Sector ID information prior to Command execution.
Execution Result R R R R R R R
No data transfer takes place. Status information after Command execution. Sector ID information after Command execution.
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PHASE Command Result
R/W W R
D7 0 1
D6 0 0
D5 0 0
VERSION DATA BUS D4 D3 D2 1 0 0 1 0 0
D1 0 0
D0 0 0
REMARKS Command Code Enhanced Controller
PHASE Command
R/W W W W W W W W W W W
D7 0 0
D6 MFM 0
FORMAT A TRACK DATA BUS D5 D4 D3 D2 D1 0 0 1 1 0 0 0 0 HDS DS1 N SC GPL D C H R N ST0 ST1 ST2 Undefined Undefined Undefined Undefined RECALIBRATE DATA BUS D4 D3 D2 D1 0 0 1 1 0 0 0 DS1
D0 1 DS0
REMARKS Command Codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters
Execution for Each Sector Repeat:
Result
R R R R R R R
FDC formats an entire cylinder Status information after Command execution
PHASE Command Execution
R/W W W
D7 0 0
D6 0 0
D5 0 0
D0 1 DS0
REMARKS Command Codes Head retracted to Track 0 Interrupt.
PHASE Command Result
R/W W R R
D7 0
D6 0
SENSE INTERRUPT STATUS DATA BUS D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 ST0 PCN
REMARKS Command Codes Status information at the end of each seek operation.
PHASE Command
R/W W W W
D7 0
SPECIFY DATA BUS D6 D5 D4 D3 D2 D1 0 0 0 0 0 1 SRT HUT HLT
D0 1 ND
REMARKS Command Codes
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PHASE Command Result
R/W W W R
D7 0 0
D6 0 0
SENSE DRIVE STATUS DATA BUS D5 D4 D3 D2 D1 0 0 0 1 0 0 0 0 HDS DS1 ST3
D0 0 DS0
REMARKS Command Codes Status information about FDD
PHASE Command Execution
R/W W W W
D7 0 0
D6 0 0
D5 0 0
SEEK DATA BUS D4 D3 D2 0 1 1 0 0 HDS NCN
D1 1 DS1
D0 1 DS0
REMARKS Command Codes Head positioned over proper cylinder on diskette.
PHASE Command
R/W W W W W
D7 0 0 0
D6 0
D5 0
CONFIGURE DATA BUS D4 D3 D2 1 0 0 0 0 POLL PRETRK
D1 1
D0 1 0
REMARKS Configure Information
0 0 EIS EFIFO
0 0 FIFOTHR
Execution
PHASE Command
R/W W W W
D7 1 0
D6 DIR 0
D5 0 0
RELATIVE SEEK DATA BUS D4 D3 D2 D1 0 1 1 1 0 0 HDS DS1 RCN DUMPREG DATA BUS D4 D3 D2 0 1 1
D0 1 DS0
REMARKS
PHASE Command
R/W W
D7 0
D6 0
D5 0
D1 1
D0 0
REMARKS *Note: Registers placed in FIFO
Execution Result
R R R R R R R R R R
PCN-Drive 0 PCN-Drive 1 PCN-Drive 2 PCN-Drive 3 SRT LOCK 0 HLT SC/EOT 0 D3 D2 D1 EIS EFIFO POLL PRETRK D0 HUT ND GAP WGATE FIFOTHR
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PHASE Command Execution
R/W W W
D7 0 0
D6 MFM 0
D5 0 0
READ ID DATA BUS D4 D3 D2 0 1 0 0 0 HDS
D1 1 DS1
D0 0 DS0
REMARKS Commands The first correct ID information on the Cylinder is stored in Data Register Status information after Command execution.
Result
R
ST0
Disk status after the Command has completed R R R R R R ST1 ST2 C H R N PERPENDICULAR MODE DATA BUS D5 D4 D3 D2 D1 0 1 0 0 1 D3 D2 D1 D0 GAP INVALID CODES DATA BUS D5 D4 D3 D2 D1 Invalid Codes ST0 LOCK DATA BUS D5 D4 D3 0 1 0 0 LOCK 0
PHASE Command
R/W W
D7 0 OW
D6 0 0
D0 REMARKS 0 Command Codes WGATE
PHASE Command Result
R/W W R
D7
D6
D0
REMARKS Invalid Command Codes (NoOp - FDC goes into Standby State) ST0 = 80H
PHASE Command Result
R/W W R
D7 LOCK 0
D6 0 0
D2 1 0
D1 0 0
D0 0 0
REMARKS Command Codes
SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write. Note: These bits are used internally only. They are not reflected in the Drive Select pins. It is the user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).
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6.11
Data Transfer Commands
All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of the command. If the seek portion fails, it is reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed.
6.11.1 Read Data
A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette matches with the sector address specified in the command, the FDC reads the sector's data field and transfers the data to the FIFO. After completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO. This continuous read function is called "Multi-Sector Read Operation". Upon receipt of the TC cycle, or an implied TC (FIFO overrun/underrun), the FDC stops sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read Data Command. N determines the number of bytes per sector (see Table 6.18 below). If N is set to zero, the sector size is set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred. Table 6.18 - Sector Sizes N 00 01 02 03 .. 07 SECTOR SIZE 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 Kbytes
The amount of data which can be handled with a single command to the FDC depends upon MT (multitrack) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1. If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 6.19.
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At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the ND bit in Status Register 1 to "1" indicating a sector not found, and terminates the Read Data Command. After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or data field, the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the DE bit flag in Status Register 1 to "1", sets the DD bit in Status Register 2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 6.20 describes the effect of the SK bit on the Read Data command execution and results. Except where noted in Table 6.20, the C or R value of the sector address is automatically incremented (see Table 6.22). Table 6.19 - Effects of MT and N Bits MT 0 1 0 1 0 1 N 1 1 2 2 3 3 MAXIMUM TRANSFER CAPACITY 256 x 26 = 6,656 256 x 52 = 13,312 512 x 15 = 7,680 512 x 30 = 15,360 1024 x 8 = 8,192 1024 x 16 = 16,384 FINAL SECTOR READ FROM DISK 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1
Table 6.20 - Skip Bit vs Read Data Command DATA ADDRESS MARK TYPE ENCOUNTERED Normal Data Deleted Data RESULTS CM BIT OF DESCRIPTION ST2 SET? OF RESULTS No Normal termination. Address not Yes incremented. Next sector not searched for. Normal No termination. Normal Yes termination. Sector not read ("skipped").
SK BIT VALUE 0 0
SECTOR READ? Yes Yes
1 1
Normal Data Deleted Data
Yes No
6.12
Read Deleted Data
This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 6.21 describes the effect of the SK bit on the Read Deleted Data command execution and results. Except where noted in Table 6.21, the C or R value of the sector address is automatically incremented (see Table 6.22).
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Table 6.21 - Skip Bit vs. Read Deleted Data Command DATA ADDRESS MARK TYPE ENCOUNTERED Normal Data RESULTS SECTOR READ? Yes CM BIT OF ST2 SET? Yes DESCRIPTION OF RESULTS Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read ("skipped"). Normal termination.
SK BIT VALUE 0
0 1
Deleted Data Normal Data
Yes No
No Yes
1
Deleted Data
Yes
No
6.13
Read A Track
This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. The FDC compares the ID information read from each sector with the specified value in the command and sets the ND flag of Status Register 1 to a "1" if there no comparison. Multi-track or skip operations are not allowed with this command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be set to "0". This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the nINDEX pin, then it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command.
Table 6.22 - Result Phase Table MT 0 HEAD 0 1 1 0 1 NC: LSB: FINAL SECTOR TRANSFERRED TO HOST Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT ID INFORMATION AT RESULT PHASE C H R N NC NC R+1 NC C+1 NC 01 NC NC NC R+1 NC C+1 NC 01 NC NC NC R+1 NC NC LSB 01 NC NC NC R+1 NC C+1 LSB 01 NC
No Change, the same value as the one at the beginning of command execution. Least Significant Bit, the LSB of H is complemented.
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6.14
Write Data
After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via the FIFO and writes it to the sector's data field. After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of the sector transfer. The Sector Number stored in "R" is incremented by one, and the FDC continues writing to the next data field. The FDC continues this "Multi-Sector Write Operation". Upon receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the DE bit of Status Register 1 to "1", and terminates the Write Data command. The Write Data command operates in much the same manner as the Read Data command. The following items are the same. Please refer to the Read Data Command for details: Transfer Capacity EN (End of Cylinder) bit ND (No Data) bit Head Load, Unload Time Interval ID information when the host terminates the command Definition of DTL when N = 0 and when N does not = 0
6.15
Write Deleted Data
This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk.
6.16
Verify
The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the previously-stored value. Because data is not transferred to the host, the TC cycle cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to "0" and the EOT value equal to the final sector to be checked. If EC is set to "0", DTL/SC should be programmed to 0FFH. Refer to Table 6.22 and Table 6.23 for information concerning the values of MT and EC versus SC and EOT value. Definitions: # Sectors Per Side = Number of formatted sectors per each side of the disk. # Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to "1".
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Table 6.23 - Verify Command Result Phase Table MT 0 0 0 0 1 1 1 1 Note: EC 0 0 1 1 0 0 1 1 SC/EOT VALUE SC = DTL EOT <= # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC <= # Sectors Remaining AND EOT <= # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side SC = DTL EOT <= # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC <= # Sectors Remaining AND EOT <= # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side TERMINATION RESULT Success Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid
If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on Side 0, verifying will continue on Side 1 of the disk.
6.17
Format A Track
The Format command allows an entire track to be formatted. After a pulse from the nINDEX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled by the values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively). After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the nINDEX pin again and it terminates the command. Table 6.24 contains typical values for gap fields that are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics.
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FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT
GAP4a 80x 4E SYNC 12x 00 IAM GAP1 SYNC 50x 12x 4E 00 IDAM C Y L H D S N C GAP2 SYNC EOR 22x 12x C C 4E 00 DATA AM C DATA R GAP3 GAP 4b C
3x FC C2
3x FE A1
3x FB A1 F8
SYSTEM 3740 (SINGLE DENSITY) FORMAT
GAP4a 40x FF SYNC 6x 00 IAM GAP1 SYNC 26x 6x FF 00 IDAM C Y L H D S N C GAP2 SYNC 11x 6x EOR C FF 00 C DATA AM C DATA R GAP3 GAP 4b C
FC
FE
FB or F8
PERPENDICULAR FORMAT
GAP4a 80x 4E SYNC 12x 00 IAM GAP1 SYNC 50x 12x 4E 00 IDAM C Y L H D S N C GAP2 SYNC EOR 41x 12x C C 4E 00 DATA AM C DATA R GAP3 GAP 4b C
3x FC C2
3x FE A1
3x FB A1 F8
Table 6.24 - Typical Values for Formatting SECTOR SIZE N SC GPL1 GPL2 09 128 00 12 07 128 00 10 10 19 512 02 08 18 30 46 87 FM 1024 03 04 2048 04 02 C8 FF 5.25" Drives C8 FF 4096 05 01 ... ... 0C 256 01 12 0A 256 01 10 20 32 512* 02 09 2A 50 03 04 80 F0 MFM 1024 2048 04 02 C8 FF 4096 05 01 C8 FF ... ... 128 0 0F 07 1B 3.5" Drives FM 256 1 09 0F 2A 512 2 05 1B 3A 256 1 0F 0E 36 MFM 512** 2 09 1B 54 1024 3 05 35 74 GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. Note: All values except sector size are in hex. FORMAT
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6.18
Control Commands
Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt.
6.18.1 Read ID
The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost.
6.18.2 Recalibrate
This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter and checks the status of the nTRK0 pin from the FDD. As long as the nTRK0 pin is low, the DIR signal remains 0 and step pulses are issued. When the nTRK0 pin goes high, the SE bit in Status Register 0 is set to "1" and the command is terminated. If the nTRK0 pin is still low after 255 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to "1" and terminates the command. Disks capable of handling more than 256 tracks per side may require more than one Recalibrate command to return the head back to physical Track 0. The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after the Recalibrate command to effectively terminate it and to provide verification of the head position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once. Upon power up, the software must issue a Recalibrate command to properly initialize all drives and the controller.
6.18.3 Seek
The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a difference: PCN < NCN: PCN > NCN: Direction signal to drive set to "1" (step in) and issues step pulses. Direction signal to drive set to "0" (step out) and issues step pulses.
The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to "1" and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once.
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Note that if implied seek is not enabled, the read and write commands should be preceded by: 1. 2. 3. 4. Seek command - Step to the proper track Sense Interrupt Status command - Terminate the Seek command Read ID - Verify head is on proper track Issue Read/Write command.
The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense Interrupt Status command is issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that the user service all pending interrupts through the Sense Interrupt Status command.
6.19
Sense Interrupt Status
An interrupt signal is generated by the FDC for one of the following reasons: 1. Upon entering the Result Phase of: a. Read Data command b. Read A Track command c. Read ID command d. Read Deleted Data command e. Write Data command f. Format A Track command g. Write Deleted Data command h. Verify command 2. End of Seek, Relative Seek, or Recalibrate command
The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt. Table 6.25 - Interrupt Identification SE 0 1 IC 11 00 INTERRUPT DUE TO Polling Normal termination of Seek or Recalibrate command Abnormal termination of Seek or Recalibrate command
1
01
The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit in ST0 will always return a "0". If a Sense Interrupt Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command.
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6.20
Sense Drive Status
Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information.
6.21
Specify
The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT (Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. The values change with the data rate speed selection and are documented in Table 6.26. The values are the same for MFM and FM. DMA operation is selected by the ND bit. When ND is "0", the DMA mode is selected. This part does not support non-DMA mode. In DMA mode, data transfers are signaled by the DMA request cycles.
6.22
Configure
The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements. Table 6.26 - Drive Control Delays (ms) 2M 64 4 .. 56 60 1M 128 8 .. 112 120 HUT 500K 300K 426 256 26.7 16 .. .. 373 224 400 240 250K 512 32 .. 448 480 2M 4 3.75 .. 0.5 0.25 HLT 00 01 02 .. 7F 7F 2M 64 0.5 1 .. 63 63.5 1M 128 1 2 .. 126 127 500K 256 2 4 .. 252 254 300K 426 3.3 6.7 .. 420 423 250K 512 4 8 . 504 508 1M 8 7.5 .. 1 0.5 SRT 500K 300K 26.7 16 25 15 .. .. 3.33 2 1.67 1 250K 32 30 .. 4 2
0 1 .. E F
6.22.1 Configure Default Values
EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte
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PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek. EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis. Defaults to "1", FIFO disabled. The threshold defaults to "1". POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired. FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes. PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255.
6.23
Version
The Version command checks to see if the controller is an enhanced type or the older type (765A). A value of 90 H is returned as the result byte.
6.24
Relative Seek
The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. DIR RCN Head Step Direction Control Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. DIR 0 1 ACTION Step Head Out Step Head In
The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped with other Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0. As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and the head is on any track (0-255). If a Seek command is issued, the head will stop at track 255. If a Relative Seek command is issued, the FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the maximum track that the FDC could position the head on using Relative Seek will be 295 (D), the initial track + 255 (D). The maximum count that the head can be moved with a single Relative Seek command is 255 (D). The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the track number goes above 255 (D). It is the user's responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track
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that it is working in an "extended track area" (greater than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will return an error if the head is farther than 255 due to its limitation of issuing a maximum of 256 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the "extended track area". It is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary. A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results which may be difficult to keep track of with software without the Read ID command.
6.25
Perpendicular Mode
The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 6.27 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0). Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The user must ensure that these two data rates remain consistent. The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The Format Fields table illustrates the change in the Gap2 field size for the perpendicular format. On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC. With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0). It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged.
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The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values. When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply: 1. 2. 3. Note: The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. The write pre-compensation given to a perpendicular mode drive will be 0ns. For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation.
Bits D0-D3 can only be overwritten when OW is programmed as a "1".If either GAP or WGATE is a "1" then D0-D3 are ignored. Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND: "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value. "Hardware" resets will clear all bits (GAP, WGATE and D0-D3) to "0", i.e all conventional mode. Table 6.27 - Effects of WGATE and GAP Bits LENGTH OF GAP2 FORMAT FIELD 22 Bytes 22 Bytes 22 Bytes 41 Bytes PORTION OF GAP 2 WRITTEN BY WRITE DATA OPERATION 0 Bytes 19 Bytes 0 Bytes 38 Bytes
WGATE
GAP
MODE
0 0 1 1
0 1 0 1
Conventional Perpendicular (500 Kbps) Reserved (Conventional) Perpendicular (1 Mbps)
6.26
Lock
In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should be used. The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware" RESET from the nPCI_RESET pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte.
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6.27
Enhanced DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands.
6.27.1 Compatibility
The LPC47M172 was designed with software compatibility in mind. It is a fully backwards- compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS.
6.28
Serial Port (UART)
The LPC47M172 incorporates two full function UARTs. They are compatible with the 16450, the 16450 ACE registers and the 16C550A. The UARTs perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, power down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UART's interrupt. The second UART also supports IrDA, HP-SIR, and ASK-IR infrared modes of operation.
Note:
Input pins of Serial Port 2 are internally pulled down to VSS only until Serial Port 2 is enabled. Once Serial Port 2 is enabled, the pull-downs are removed until VTR POR.
6.28.1 Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial port is defined by the configuration registers (see "Configuration" section). The Serial Port registers are located at sequentially increasing addresses above these base addresses (see Table 6.28). Table 6.28 - Addressing the Serial Port DLAB* 0 0 0 X X X X X X A2 0 0 0 0 0 0 1 1 1 A1 0 0 0 1 1 1 0 0 1 A0 0 0 1 0 0 1 0 1 0 REGISTER NAME Receive Buffer (read) Transmit Buffer (write) Interrupt Enable (read/write) Interrupt Identification (read) FIFO Control (write) Line Control (read/write) Modem Control (read/write) Line Status (read/write) Modem Status (read/write)
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DLAB* X 1 1 *Note:
A2 1 0 0
A1 1 0 0
A0 1 0 1
REGISTER NAME Scratchpad (read/write) Divisor LSB (read/write) Divisor MSB (read/write
DLAB is Bit 7 of the Line Control Register The following section describes the operation of the registers.
6.28.2 Receive Buffer Register (RB)
Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible.
6.28.3 Transmit Buffer Register (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete.
6.28.4 Interrupt Enable Register (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47M172. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. Bit 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1". Bit 1 This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1". Bit 2 This bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source.
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Bit 3 This bit enables the MODEM Status Interrupt when set to logic "1". This is caused when one of the Modem Status Register bits changes state. Bits 4 through 7 These bits are always logic "0".
6.28.5 FIFO Control Register (FCR)
Address Offset = 2H, DLAB = X, WRITE This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported. The UART is shadowed in the UART1 FIFO Control Shadow Register (Power Control/Runtime Register at offset 0x1A). Bit 0 Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0" disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed. Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 3 Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip. Bit 4,5 Reserved Bit 6,7 These bits are used to set the trigger level for the RCVR FIFO interrupt.
6.28.6 Interrupt Identification Register (IIR)
Address Offset = 2H, DLAB = X, READ By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority: 1. 2. 3. 4. Receiver Line Status (highest priority) Received Data Ready Transmitter Holding Register Empty MODEM Status (lowest priority)
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Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR are described below. Bit 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending. Bits 1 and 2 These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table. Bit 3 In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending. Bits 4 and 5 These bits of the IIR are always logic "0". Bits 6 and 7 These two bits are set when the FIFO CONTROL Register bit 0 equals 1. Bit 7 0 0 1 1 RCVR FIFO Bit 6 Trigger Level (BYTES) 0 1 1 4 0 8 1 14
Table 6.29 - Interrupt Control Table FIFO MODE ONLY BIT 3 0 0 INTERRUPT IDENTIFICATION REGISTER BIT 2 0 1 BIT 1 0 1 BIT 0 1 0 PRIORIT Y LEVEL Highest
0
1
0
0
Second
INTERRUPT SET AND RESET FUNCTIONS INTERRUPT INTERRUPT INTERRUPT RESET TYPE SOURCE CONTROL None None Overrun Error, Receiver Line Parity Error, Reading the Line Status Framing Error or Status Register Break Interrupt Read Receiver Received Data Receiver Data Buffer or the FIFO Available Available drops below the trigger level.
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FIFO MODE ONLY
INTERRUPT IDENTIFICATION REGISTER
1
1
0
0
0
0
1
0
0
0
0
0
INTERRUPT SET AND RESET FUNCTIONS No Characters Have Been Removed From or Input to the Character Reading the RCVR FIFO Second Timeout Receiver Buffer during the last 4 Indication Register Char times and there is at least 1 char in it during this time Reading the IIR Register (if Transmitter Transmitter Source of Holding Third Holding Register Interrupt) or Register Empty Writing the Empty Transmitter Holding Register Clear to Send or Data Set Ready Reading the MODEM Fourth MODEM Status or Ring Indicator Status or Data Carrier Register Detect
6.28.7 Line Control Register (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
Start LSB Data 5-8 bits MSB Parity Stop
Serial Data This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows: The Start, Stop and Parity bits are not included in the word length. BIT 1 0 0 1 1 Bit 2 This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information. BIT 0 0 1 0 1 WORD LENGTH 5 Bits 6 Bits 7 Bits 8 Bits
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BIT 2 0 1 1 1 1 Note: Bit 3
WORD LENGTH -5 bits 6 bits 7 bits 8 bits
NUMBER OF STOP BITS 1 1.5 2 2 2
The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). Bit 4 Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. Bit 5 This bit is the Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or Space Parity. When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as a 0 (Space Parity). If bits 3 and 5 are 1 and bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark Parity). If bit 5 is 0 Stick Parity is disabled. Bit 6 Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the Spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. Bit 7 Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register.
6.28.8 Modem Control Register (MCR)
Address Offset = 4H, DLAB = X, READ/WRITE This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1". Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0.
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Bit 2 This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. Bit 3 Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled. Bit 4 This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occur: 1. 2. 3. 4. 5. 6. 7. The TXD is set to the Marking State(logic "1"). The receiver Serial Input (RXD) is disconnected. The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI, DCD). The Modem Control output pins are forced inactive high. Data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. Bits 5 through 7 These bits are permanently set to logic zero.
6.28.9 Line Status Register (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE Bit 0 Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all of the data in the Receive Buffer Register or the FIFO. Bit 1 Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrun error will occur only when the FIFO is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the Line Status Register is read. Bit 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is
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associated with the particular character in the FIFO it applies to. associated character is at the top of the FIFO. Bit 3
This error is indicated when the
Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this `start' bit twice and then takes in the `data'. Bit 4 Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be logic "1" for at least 1/2 bit time. Note: Bit 5 Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic "0" whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is a read only bit. Bit 6 Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty, Bit 7 This bit is permanently set to logic "0" in the 450 mode. In the FIFO mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO. Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled.
6.28.10 Modem Status Register (MSR)
Address Offset = 6H, DLAB = X, READ/WRITE This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read.
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Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. Bit 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to logic "1". Bit 3 Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state. Note: Bit 4 This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR. Bit 5 This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to DTR in the MCR. Bit 6 This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR. Bit 7 This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT2 in the MCR. Whenever bit 0, 1, 2, or 3 is set to a logic "1", a MODEM Status Interrupt is generated.
6.28.11 Scratchpad Register (SCR)
Address Offset =7H, DLAB =X, READ/WRITE This 8 bit read/write register has no effect on the operation of the Serial Port. scratchpad register to be used by the programmer to hold data temporarily. It is intended as a
6.29
Programmable Baud Rate Generator (And Divisor Latches DLH, DLL)
The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal PLL clock by any divisor from 1 to 65535. The internal PLL clock is divided down to generate a 1.8462MHz frequency for Baud Rates less than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz frequency for 230.4k and a 7.3728MHz frequency for 460.8k. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is
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loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock. Table 6.30 shows the baud rates possible.
6.29.1 Effect Of The Reset on Register File
The Reset Function (details the effect of the Reset input on each of the registers of the Serial Port.
6.29.2 FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. B. The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is cleared as soon as the FIFO drops below its programmed trigger level. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the FIFO drops below the trigger level.
C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows: A. A FIFO timeout interrupt occurs if all the following conditions exist: At least one character is in the FIFO. The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are programmed, the second one is included in this time delay). The most recent CPU read of the FIFO was longer than 4 continuous character times ago. This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character. B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baud rate).
C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the CPU reads the RCVR FIFO. When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows: A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.
B.
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.
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6.29.3 FIFO Polled Mode Operation
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: Bit 0=1 as long as there is one byte in the RCVR FIFO. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode, the IIR is not affected since EIR bit 2=0. Bit 5 indicates when the XMIT FIFO is empty. Bit 6 indicates that both the XMIT FIFO and shift register are empty. Bit 7 indicates whether there are any errors in the RCVR FIFO. There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. Table 6.30 - Baud Rates DESIRED BAUD RATE 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 230400 460800 Note1: Note :
2
DIVISOR USED TO GENERATE 16X CLOCK 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 32770 32769
PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL1 0.001 0.004 0.005 0.030 0.16 0.16 0.16 0.16
HIGH SPEED BIT2 X X X X X X X X X X X X X X X X X X X 1 1
The percentage error for all baud rates, except where indicated otherwise, is 0.2%. The High Speed bit is located in the Device Configuration Space.
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Table 6.31 - Reset Function Table REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO RESET CONTROL RESET RESET RESET RESET RESET RESET RESET RESET RESET/Read LSR RESET/Read RBR RESET/ReadIIR/Write THR RESET RESET RESET RESET RESET/ FCR1*FCR0/_FCR0 RESET/ FCR1*FCR0/_FCR0 RESET STATE All bits low Bit 0 is high; Bits 1 - 7 low All bits low All bits low All bits low All bits low except 5, 6 high Bits 0 - 3 low; Bits 4 - 7 input High Low Low Low High High High High All Bits Low All Bits Low
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Table 32 - Register Summary for an Individual UART Channel REGISTER ADDRESS
(Note 1)
REGISTER NAME
Receive Buffer Register (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register
REGISTER SYMBOL
RBR THR IER
BIT 0
Data Bit 0
(Note 2)
BIT 1
Data Bit 1 Data Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETHREI) Interrupt ID Bit RCVR FIFO Reset Word Length Select Bit 1 (WLS1)
BIT 2
Data Bit 2 Data Bit 2 Enable Receiver Line Status Interrupt (ELSI)
BIT 3
Data Bit 3 Data Bit 3 Enable MODEM Status Interrupt (EMSI)
BIT 4
Data Bit 4 Data Bit 4 0
BIT 5
Data Bit 5 Data Bit 5 0
BIT 6
Data Bit 6 Data Bit 6 0
BIT 7
Data Bit 7 Data Bit 7 0
ADDR = 0 DLAB = 0 ADDR = 0 DLAB = 0 ADDR = 1 DLAB = 0
Data Bit 0 Enable Received Data Available Interrupt (ERDAI) "0" if Interrupt Pending
ADDR = 2
Interrupt Ident. Register (Read Only)
IIR
Interrupt ID Bit XMIT FIFO Reset Number of Stop Bits (STB) OUT1
(Note 4)
Interrupt ID Bit (Note 6) DMA Mode Select
(Note 7)
0
0
FIFOs Enabled
(Note 6)
FIFOs Enabled
(Note 6)
ADDR = 2
FIFO Control Register (Write Only)
FCR (Note 8) FIFO Enable
Reserved
Reserved
RCVR Trigger RCVR LSB Trigger MSB Set Break Divisor Latch Access Bit (DLAB) 0 Error in RCVR FIFO
(Note 6)
ADDR = 3
Line Control Register
LCR
Word Length Select Bit 0 (WLS0)
Parity Enable (PEN) OUT2
(Note 4)
Even Parity Select (EPS) Loop Break Interrupt (BI) Clear to Send (CTS)
Stick Parity
ADDR = 4 ADDR = 5
MODEM Control Register Line Status Register
MCR LSR
Data Terminal Request to Ready (DTR) Send (RTS) Data Ready (DR) Overrun Error (OE)
0 Transmitter Holding Register (THRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13
0 Transmitter Empty (TEMT)
(Note 3)
Parity Error (PE)
Framing Error (FE)
ADDR = 6
MODEM Status Register
MSR
Delta Clear to Send (DCTS)
Delta Data Set Ready (DDSR) Bit 1 Bit 1 Bit 9
ADDR = 7 ADDR = 0 DLAB = 1 ADDR = 1 DLAB = 1
Scratch Register (Note 5) Divisor Latch (LS) Divisor Latch (MS)
SCR DDL DLM
Bit 0 Bit 0 Bit 8
Trailing Edge Ring Indicator (TERI) Bit 2 Bit 2 Bit 10
Delta Data Carrier Detect (DDCD) Bit 3 Bit 3 Bit 11
Ring Indicator (RI)
Bit 4 Bit 4 Bit 12
Bit 6 Bit 6 Bit 14
Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15
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Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8
DLAB is Bit 7 of the Line Control Register (ADDR = 3). Bit 0 is the least significant bit. It is the first bit serially transmitted or received. When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. This bit no longer has a pin associated with it. When operating in the XT mode, this register is not available. These bits are always zero in the non-FIFO mode. Writing a one to this bit has no effect. DMA modes are not supported in this chip. The UART1 and UART2 FCR's are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21).
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Chapter 7
7.1
7.1.1
Notes On Serial Port Operation
FIFO Mode Operation:
General
The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.
7.1.2
TX and RX FIFO Operation
The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have been loaded into the FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated without a one character delay. Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs. One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a timeout interrupt. The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud).
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7.2
Infrared Interface
The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Several IR implementations have been provided for the second UART in this chip, IrDA, HP-SIR and Amplitude Shift Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins or optional IRTX2 and IRRX2 pins. These can be selected through the configuration registers. IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit time. A one is signaled by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the IrDA waveform. The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a 500KHz waveform for the duration of the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for the parameters of the ASK-IR waveform. If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The IR half duplex time-out is programmable via CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments. IR Transmit Pins The following description pertains to the TXD2 and IRTX2 pins of the LPC47M172. Following a VCC POR, the TXD2 and IRTX2 pins will be output and low. They will remain low until one of the following conditions are met: IRTX2 Pin 1. This pin will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the IR transmit output of the IRCC block.
TXD2 Pin 1. This pin will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the IR transmit output of the IRCC block (if IR is enabled through the IR Option Register for Serial Port 2). This pin will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of serial port 2.
2.
7.3
Parallel Port
The LPC47M172 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation.
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The Parallel Port configuration registers are summarized in Table 11.2 in the "Configuration" section. The Parallel Port logical device configuration registers (0xF0 and 0xF1) are defined in Table 11.11. The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power-up. The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the Parallel Port is shown below: DATA PORT STATUS PORT CONTROL PORT EPP ADDR PORT BASE ADDRESS + 00H BASE ADDRESS + 01H BASE ADDRESS + 02H BASE ADDRESS + 03H EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA PORT 3 BASE ADDRESS + 04H BASE ADDRESS + 05H BASE ADDRESS + 06H BASE ADDRESS + 07H
The bit map of these registers is: D0 PD0 TMOUT D1 PD1 0 D2 PD2 0 nINIT PD2 PD2 PD2 PD2 PD2 D3 PD3 nERR SLC PD3 PD3 PD3 PD3 PD3 D4 PD4 SLCT IRQE PD4 PD4 PD4 PD4 PD4 D5 PD5 PE PCD PD5 PD5 PD5 PD5 PD5 D6 PD6 nACK 0 PD6 PD6 PD6 PD6 PD6 D7 NOTE PD7 1 nBUSY 1 0 PD7 PD7 PD7 PD7 PD7 1 2 2 2 2 2
DATA PORT STATUS PORT CONTROL PORT EPP ADDR PORT EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA PORT 3 Note 1: Note 2:
STROBE AUTOFD PD0 PD0 PD0 PD0 PD0 PD1 PD1 PD1 PD1 PD1
These registers are available in all modes. These registers are only available in EPP mode.
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Table 7.1 - Parallel Port Connector HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft. SMSC PIN NUMBER See Chapter 3 Description of Pin Functions. STANDARD nSTROBE PD<0:7> nACK BUSY PE SLCT nALF nERROR nINITP nSLCTIN EPP nWrite PData<0:7> Intr nWait (User Defined) (User Defined) nDatastb (User Defined) nRESET nAddrstrb ECP nStrobe PData<0:7> nAck Busy, PeriphAck(3) PError, nAckReverse (3) Select nAutoFd, HostAck(3) nFault (1) nPeriphRequest (3) nInit(1) nReverseRqst(3) nSelectIn(1,3)
7.4
7.4.1
IBM XT/AT Compatible, Bi-Directional and EPP Modes
Data Port
ADDRESS OFFSET = 00H The Data Port is located at an offset of `00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU.
7.4.2
Status Port
ADDRESS OFFSET = 01H The Status Port is located at an offset of `01H' from the base address. The contents of this register are latched for the duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Serial Port Logical Device Configuration Registers) is `0', writing a one to this bit clears the TMOUT status bit. Writing a zero to this bit has no effect. If the TIMEOUT_SELECT bit (bit 4 of the
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Parallel Port Mode Register 2, 0xF1 in Serial Port Logical Device Configuration Registers) is `1', the TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register. BITS 1, 2 Are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. BIT 3 nERR - nERROR The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has been detected; a logic 1 means no error has been detected. BIT 4 SLT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on line; a logic 0 means it is not selected. BIT 5 PE - PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper. BIT 6 nACK - ACKNOWLEDGE The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer has received a character and can now accept another. A logic 1 means that it is still processing the last character or has not received the data. BIT 7 nBUSY - nBUSY The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic 1 means that it is ready to accept the next character.
7.4.3
Control Port
ADDRESS OFFSET = 02H The Control Port is located at an offset of `02H' from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - INITIATE OUTPUT This bit is output onto the nINITP output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected.
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BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled. BIT 5 PCD - PARALLEL CONTROL DIRECTION Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). Bits 6 and 7 during a read are a low level, and cannot be written.
7.4.4
EPP Address Port
ADDRESS OFFSET = 03H The EPP Address Port is located at an offset of `03H' from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP ADDRESS WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register is only available in EPP mode.
7.4.5
EPP Data Port 0
ADDRESS OFFSET = 04H The EPP Data Port 0 is located at an offset of `04H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP DATA WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP mode.
7.4.6
EPP Data Port 1
ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of `05H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.
7.4.7
EPP Data Port 2
ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of `06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.
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7.4.8
EPP Data Port 3
ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of `07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.
7.5
EPP 1.9 Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted.
7.5.1
Software Constraints
Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (i.e., a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic "1", and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the parallel bus, no error is indicated.
7.6
EPP 1.9 Write
The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address cycle. The chip inserts wait states into the LPC I/O write cycle until it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances: 1. 2. If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive.
Write Sequence of Operation 1. 2. 3. 4. 5. The host initiates an I/O write cycle to the selected EPP register. If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has not already done so, the peripheral should latch the information byte now.
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b) 7. 8.
The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that no more wait states are required followed by the TAR to complete the write cycle.
Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. Chip may modify nWRITE and nPDATA in preparation for the next cycle.
7.7
EPP 1.9 Read
The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states into the LPC I/O read cycle until it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances: 1. 2. If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nWRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive.
Read Sequence of Operation 1. 2. 3. 4. 5. 6. The host initiates an I/O read cycle to the selected EPP register. If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip tri-states the PData bus and deasserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. Peripheral drives PData bus valid. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB or nADDRSTRB. This marks the beginning of the termination phase. The chip drives the sync that indicates that no more wait states are required and drives valid data onto the LAD[3:0] signals, followed by the TAR to complete the read cycle.
7. a) b) 8. 9.
Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tristated. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.
7.8
EPP 1.7 Operation
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to the end of the cycle. If a time-out occurs, the current EPP cycle is aborted and the timeout condition is indicated in Status bit 0.
7.8.1
Software Constraints
Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read.
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7.9
EPP 1.7 Write
The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The chip inserts wait states into the I/O write cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high. Write Sequence of Operation 1. 2. 3. 4. 5. 6. 7. The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE. The host initiates an I/O write cycle to the selected EPP register. The chip places address or data on PData bus. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts nWAIT or a time-out occurs. The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the internal data bus for the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
7.10
EPP 1.7 Read
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high. Read Sequence of Operation 1. 2. 3. 4. 5. 6. 7. 8. 9. The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus. The host initiates an I/O read cycle to the selected EPP register. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts nWAIT or a time-out occurs. The Peripheral drives PData bus valid. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. The chip drives the final sync and deasserts nDATASTB or nADDRSTRB. Peripheral tri-states the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. Table 7.2 - EPP Pin Descriptions EPP SIGNAL nWRITE PD<0:7> INTR EPP NAME nWrite Address/Data Interrupt TYPE O I/O I EPP DESCRIPTION This signal is active low. It denotes a write operation. Bi-directional EPP byte wide address and data bus. This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP).
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EPP SIGNAL nWAIT
EPP NAME nWait
TYPE I
nDATASTB nRESET nADDRSTB PE SLCT
nData Strobe nReset Address Strobe Paper End Printer Selected Status Error
O O O I I
EPP DESCRIPTION This signal is active low. It is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer. This signal is active low. It is used to denote data read or write operation. This signal is active low. When driven active, the EPP device is reset to its initial operational mode. This signal is active low. It is used to denote address read or write operation. Same as SPP mode. Same as SPP mode.
nERR Note 1: Note 2:
I
Same as SPP mode.
SPP and EPP can use 1 common register. nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required to be a low.
7.10.1 Extended Capabilities Parallel Port
ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer capability.
7.10.2 Vocabulary
The following terms are used in this document: assert: forward: reverse: Pword: 1 0 When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. Host to Peripheral communication. Peripheral to Host communication A port word; equal in size to the width of the LPC interface. For this implementation, PWord is always 8 bits. A high level. A low level.
These terms may be considered synonymous: PeriphClk, nAck HostAck, nAutoFd PeriphAck, Busy nPeriphRequest, nFault
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nReverseRequest, nInit nAckReverse, PError Xflag, Select ECPMode, nSelectln HostClk, nStrobe Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14, 1993. This document is available from Microsoft.
The bit map of the Extended Parallel Port registers is: data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr Note 1: Note 2: Note 3: D7 PD7 Addr/RLE nBusy 0 D6 PD6 nAck 0 D4 D3 D2 D1 D0 PD4 PD3 PD2 PD1 PD0 Address or RLE field PError Select nFault 0 0 0 Direction ackIntEn SelectI nInit autofd strobe n Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 1 0 0 0 0 Parallel Port IRQ Parallel Port DMA full empty nErrIntrE dmaEn serviceIntr n D5 PD5 NOTE 2 1 1 2 2 2
0 0 compress intrValue MODE
These registers are available in all modes. All FIFOs use one common 16 byte FIFO. The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration Registers.
7.11
ECP Implementation Standard
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft.
7.11.1 Description
The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions. Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the
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next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional.
Table 7.3 - ECP Pin Descriptions NAME nStrobe PData 7:0 nAck PeriphAck (Busy) TYPE O I/O I I DESCRIPTION During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in the forward direction. In the reverse direction this signal indicates whether the data lines contain ECP command information or data. The peripheral uses this signal to flow control in the forward direction. It is an "interlocked" handshake with nStrobe. PeriphAck also provides command information in the reverse direction. Used to acknowledge a change in the direction the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. It is an "interlocked" handshake with nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when asserted, handshaking with nAck in the reverse direction. In the forward direction this signal indicates whether the data lines contain ECP address or data. The host drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with nAck. HostAck also provides command information in the forward phase. Generates an error interrupt when asserted. This signal provides a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP Mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. The request is merely a "hint" to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU. Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. Always deasserted in ECP mode.
PError (nAckReverse)
I
Select nAutoFd (HostAck)
I O
nFault (nPeriphRequest)
I
nInit
O
nSelectIn
O
7.12
Register Definitions
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr. The table below lists these dependencies. Operation of the devices in modes other that those specified is undefined.
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Table 7.4 - ECP Register Definitions NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr Note 1: Note 2: ADDRESS (Note 1) +000h R/W +000h R/W +001h R/W +002h R/W +400h R/W +400h R/W +400h R/W +400h R +401h R/W +402h R/W ECP MODES 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register
These addresses are added to the parallel port base address as selected by configuration register or jumpers. All addresses are qualified with AEN. Refer to the AEN pin definition. Table 7.5 - Mode Descriptions MODE 000 001 010 011 100 101 110 111 DESCRIPTION* SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode EPP mode (If this option is enabled in the configuration registers) Reserved Test mode Configuration mode
*Refer to ECR Register Description
7.12.1 Data and ecpAFifo Port
ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of `00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU. Mode 011 (ECP FIFO - Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet .
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7.12.2 Device Status Register (dsr)
ADDRESS OFFSET = 01H The Status Port is located at an offset of `01H' from the base address. Bits0 - 2 are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows: BIT 3 nFault The level on the nFault input is read by the CPU as bit 3 of the Device Status Register. BIT 4 Select The level on the Select input is read by the CPU as bit 4 of the Device Status Register. BIT 5 PError The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register. BIT 6 nAck The level on the nAck input is read by the CPU as bit 6 of the Device Status Register. BIT 7 nBusy The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register.
7.12.3 Device Control Register (dcr)
ADDRESS OFFSET = 02H The Control Register is located at an offset of `02H' from the base address. The Control Register is initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - INITIATE OUTPUT This bit is output onto the nINITP output without inversion. BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts.
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BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). BITS 6 and 7 during a read are a low level, and cannot be written.
7.12.4 CFIFO (Parallel Port Data FIFO)
ADDRESS OFFSET = 400h Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction.
7.12.5 ECPDFIFO (ECP Data FIFO)
ADDRESS OFFSET = 400H Mode = 011 Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system.
7.12.6 tFifo (Test FIFO Mode)
ADDRESS OFFSET = 400H Mode = 110 Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines. The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read again. The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics. The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits. The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached.
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The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written.
7.12.7 cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H Mode = 111 This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte)
7.12.8 cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H Mode = 111 BIT 7 compress This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression. BIT 6 intrValue Returns the value of the interrupt to determine possible conflicts. BIT [5:3] Parallel Port IRQ (read-only) to Table 7.7 - Programming for Configuration Register B (Bits 5:3) BITS [2:0] Parallel Port DMA (read-only) to Table 7.8 - Programming for Configuration Register B (Bits 2:0)
7.12.9 ecr (Extended Control Register)
ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions. BITS 7,6,5 These bits are Read/Write and select the Mode.
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BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: 0: Disables the interrupt generated on the asserting edge of nFault. Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr.
BIT 3 dmaEn Read/Write 1: 0: BIT 2 serviceIntr Read/Write 1: 0: Disables DMA and all of the service interrupts. Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not cause an interrupt. Enables DMA (DMA starts when serviceIntr is 0). Disables DMA unconditionally.
case dmaEn=1: During DMA (this bit is set to a 1 when terminal count is reached). case dmaEn=0 direction=0: This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO. case dmaEn=0 direction=1: This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. BIT 1 full Read only 1: 0: BIT 0 empty Read only 1: 0: The FIFO is completely empty. The FIFO contains at least 1 byte of data. The FIFO cannot accept another byte or the FIFO is completely full. The FIFO has at least 1 free byte.
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Table 7.6 - Extended Control Register R/W 000: MODE Standard Parallel Port Mode . In this mode the FIFO is reset and common drain drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode. PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull). Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull). ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull). Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in Parallel Port configuration register CRF0. All drivers have active pull-ups (push-pull). Reserved Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull). Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). Table 7.7 - Programming for Configuration Register B (Bits 5:3) IRQ SELECTED 15 14 11 10 9 7 5 All Others CONFIG REG B BITS 5:3 110 101 100 011 010 001 111 000
001:
010:
011:
100: 101: 110: 111:
Table 7.8 - Programming for Configuration Register B (Bits 2:0) DMA SELECTED 3 2 1 All Others CONFIG REG B BITS 2:0 011 010 001 000
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7.13
Operation
7.13.1 Mode Switching/Software Control
Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010). Setting the mode to 011 or 010 will cause the hardware to initiate data transfer. If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can only be changed in mode 001. Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case all control signals will be deasserted before the mode switch. In an ecp reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic hardware ecp reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake signals if the software meets the constraints above.
7.14
ECP Operation
Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it is necessary to initialize some of the port bits. The following are required: Set Direction = 0, enabling the drivers. Set strobe = 0, causing the nStrobe signal to default to the deasserted state. Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively. Note that all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction. The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty. ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000.
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7.15
Termination from ECP Mode
Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction.
7.16
Command/Data
ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands. When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred when HostAck is low. The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address. When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware. Table 7.9 - Channel/Data Commands supported in ECP mode Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) D7 D[6:0] 0 Run-Length Count (0-127) (mode 0011 0X00 only) 1 Channel Address (0-127)
7.17
Data Compression
The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided.
7.18
Pin Definition
The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-drain in mode 000 and are push-pull in all other modes.
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7.19
LPC Connections
The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section). Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals.
7.20
Interrupts
The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 serviceIntr = 0 Disables the DMA and all of the service interrupts. Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupts generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold.
An interrupt is generated when: 1. 2. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received. For Programmed I/O: a. When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold or more free bytes in the FIFO. When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes in the FIFO.
b.
3. 4.
When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and nFault is asserted. When ackIntEn is 1 and the nAck signal transitions from a low to a high.
7.21
FIFO Operation
The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or DMA cycle depending on the selection of DMA or Programmed I/O mode. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests.
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7.21.1 DMA Transfers
DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers from the host by encoding the nLDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests a DMA cycle shall not be requested for more than 32 DMA cycles in a row. The FIFO is enabled directly by the host initiating a DMA cycle for the requested channel, and addresses need not be valid. An interrupt is generated when a TC cycle is received. (Note: The only way to properly terminate DMA transfers is with a TC cycle.) DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0.
7.21.2 DMA Mode - Transfers from the FIFO to the Host
(Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.) The ECP requests a DMA cycle whenever there is data in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The ECP stops requesting DMA cycles when the FIFO becomes empty or when a TC cycle is received, indicating that no more data is required. If the ECP stops requesting DMA cycles due to the FIFO going empty, then a DMA cycle is requested again as soon as there is one byte in the FIFO. If the ECP stops requesting DMA cycles due to the TC cycle, then a DMA cycle is requested again when there is one byte in the FIFO, and serviceIntr has been re-enabled.
7.21.3 Programmed I/O Mode or Non-DMA Mode
The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.
7.21.4 Programmed I/O - Transfers from the FIFO to the Host
In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. readIntrThreshold =(16-) data bytes in FIFO
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An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16-). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO). The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16-) bytes may be read from the FIFO in a single burst.
7.21.5 Programmed I/O - Transfers from the Host to the FIFO
In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes. writeIntrThreshold = (16-) free bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to . (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The host must respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16-) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the FIFO.
7.22
Power Management
Direct power management capability is provided for the following logical devices: floppy disk, UART, and the parallel port. Direct power management is controlled by CR22. Refer to CR22 in Table 11.3 for more information. Note on FDC Direct Powerdown: The Direct powerdown mode requires at least 8us delay at 250K bits/sec configuration and 4us delay at 500K bits/sec. The delay should be added so that the internal microcontroller can prepare itself to accept commands.
7.23
Serial IRQ
The LPC47M172 supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
7.23.1 Timing Diagrams For SER_IRQ Cycle
A) Start Frame timing with source sampled a low pulse on IRQ1
SL
or
START FRAME H R T
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME S R T S R T S R T
H PCI_CLK SER_IRQ Drive Source
Note: IRQ1
START
1
Host Controller
None
IRQ1
None
H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
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Note 1:
Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy in a synchronous bridge design. B) Stop Frame Timing with Host using 17 SER_IRQ sampling period
IRQ14 FRAME SRT PCI_CLK SER_IRQ Driver
Note: Note 1:
IRQ15 FRAME SRT
IOCHCK# FRAME SRT
STOP FRAME
NEXT CYCLE T
I
2
H
R
STOP1 None IRQ15 None Host Controller
START 3
H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle The next SER_IRQ cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stop Frame. There may be none, one or more Idle states during the Stop Frame. Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
Note 2: Note 3:
7.23.2 SER_IRQ Cycle Control
There are two modes of operation for the SER_IRQ Start Frame: 1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated without at any time driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is Idle between Stop and Start Frames. The SER_IRQ is Active between Start and Stop Frames. This mode of operation allows the SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time. Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock and will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock, then tri-state. If LPC47M172 detects any transition on an IRQ/Data line for which it is responsible, it initiates a Start Frame in order to update the Host Controller unless the SER_IRQ is already in an SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle 2) Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line information. All other SER_IRQ agents become passive and may not initiate a Start Frame. SER_IRQ will be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be used to stop or idle the SER_IRQ or the Host Controller can operate SER_IRQ in a continuous mode by initiating a Start Frame at the end of every Stop Frame. An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ bus is defaulted to Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves must continuously sample the Stop Frames pulse width to determine the next SER_IRQ Cycle's mode.
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7.23.3 SER_IRQ Data Frame
Once a Start Frame has been initiated, the LPC47M172 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase the LPC47M172 drives the SER_IRQ low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high, SER_IRQ is left tri-stated. During the Recovery phase the LPC47M172 drives the SER_IRQ high, if and only if, it had driven the SER_IRQ low during the previous Sample Phase. During the Turn-around Phase the LPC47M172 tri-states the SER_IRQ. The LPC47M172 drives the SER_IRQ line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame. The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is th the sixth IRQ/Data Frame, (6 x 3) - 1 = 17 clock after the rising edge of the Start Pulse). SER_IRQ Sampling Periods SIGNAL SAMPLED Not Used IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15
SER_IRQ PERIOD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
# OF CLOCKS PAST START 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47
SER_IRQ Period 14 is used to transfer IRQ13. Logical devices FDC, Parallel Port, Serial Port, and Keyboard have IRQ13 as a choice for their primary interrupt.
7.23.4 Stop Cycle Control
Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low for two or three clocks. If the Stop Frame's low time is two clocks then the next SER_IRQ Cycle's sampled mode is the Quiet mode; and any SER_IRQ device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame's pulse. If the Stop Frame's low time is three clocks then the next SER_IRQ Cycle's sampled mode is the Continuous mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame's pulse.
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7.23.5 Latency
Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84S with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses.
7.23.6 EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out of order.
7.23.7 AC/DC Specification Issue
All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus clock. The SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained tri-state.
7.23.8 Reset and Initialization
The SER_IRQ bus uses nPCI_RESET as its reset signal. The SER_IRQ pin is tri-stated by all agents while nPCI_RESET is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system's IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is Host Controller's responsibility to provide the default values to 8259's and other system logic before the first SER_IRQ Cycle is performed. For SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before the system configuration changes.
7.24
Interrupt Generating Registers
The LPC47M172 contains on-chip Interrupt Generating Registers to enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface. These registers, INT_GEN1 and INT_GEN2, are located in the Power Control Block/Runtime Register Block, at offsets 0x1B and 0x1C, respectively, from the base address setting (set at Index 0x60 and 0x61 Configuration Registers). See Chapter 8 Power Control Runtime Registers and Chapter 10 Runtime Register Block Runtime Registers. Registers INT_GEN1 and INT_GEN2 are enabled to output to the Serial IRQ stream by setting Power Control Block Configuration Register, at Index 0xF1, Bit [0] to `1'. When Bit [0] is set to `0', INT_GEN1 and INT_GEN2 are prevented from outputting to the Serial IRQ stream. Writing Bits 0 through 7 to `0' in registers INT_GEN1 and INT_GEN2 enable the corresponding interrupt (INT1 through INT15) to be asserted (made active) in the Serial IRQ stream. Producing an interrupt in the Serial IRQ stream by writing these bits to `0' overrides other interrupt sources for the Serial IRQ stream. No other functional logic in the LPC47M172 sets bits in these registers. The asserted interrupt in the Serial IRQ stream from registers INT_GEN1 and INT_GEN2 is removed by writing the corresponding bit to `1'.
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7.25
8042 Keyboard Controller Description
The LPC47M172 is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. This section concentrates on the LPC47M172 enhancements to the 8042. For general information about the 8042, refer to the "Hardware Description of the 8042" in the 8-Bit Embedded Controller Handbook.
8042A
P27 P10 P26 TST0 P23 TST1 P22 P11
LS05 KDAT KCLK MCLK MDAT
Keyboard and Mouse Interface
KIRQ is the Keyboard IRQ MIRQ is the Mouse IRQ Port 21 is used to create a GATEA20 signal from the LPC47M172.
7.25.1 Keyboard Interface
The LPC47M172 LPC interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data signals; the read and write signals and the Status register, Input Data register, and Output Data register. Table 7.10 shows how the interface decodes the control signals. In addition to the above signals, the host interface includes keyboard and mouse IRQs. Table 7.10 - I/O Address Map ADDRESS 0x60 0x64 Note 1: COMMAND Write Read Write Read BLOCK KDATA KDATA KDCTL KDCTL FUNCTION (NOTE 1) Keyboard Data Write (C/D=0) Keyboard Data Read Keyboard Command Write (C/D=1) Keyboard Status Read
These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read.
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7.25.2 Keyboard Data Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF bit is set.
7.25.3 Keyboard Data Read
This is an 8 bit read only register. If enabled by "ENABLE FLAGS", when read, the KIRQ output is cleared and the OBF flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be cleared in software.
7.25.4 Keyboard Command Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and the IBF bit is set.
7.25.5 Keyboard Status Read
This is an 8 bit read only register. Refer to the description of the Status Register for more information.
7.25.6 CPU-to-Host Communication
The LPC47M172 CPU can write to the Output Data register via register DBB. A write to this register automatically sets Bit 0 (OBF) in the Status register. See Table 7.11. Table 7.11 - Host Interface Flags 8042 INSTRUCTION OUT DBB FLAG Set OBF, and, if enabled, the KIRQ output signal goes high
7.25.7 Host-to-CPU Communication
The host system can send both commands and data to the Input Data register. The CPU differentiates between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is "1", the CPU interprets the register contents as a command. When bit 3 is "0", the CPU interprets the register contents as data. During a host write operation, bit 3 is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0.
7.25.8 KIRQ
If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be connected to system interrupt to signify that the LPC47M172 CPU has written to the output data register via "OUT DBB,A". If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes "DBB". (KIRQ is normally selected as IRQ1 for keyboard support.) If "EN FLAGS" has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to P24 forces KIRQ low; a high forces KIRQ high.
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7.25.9 MIRQ
If "EN FLAGS" has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal can be connected to system interrupt to signify that the LPC47M172 CPU has read the DBB register. If "EN FLAGS" has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces MIRQ low, a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support). Gate A20 A general purpose P21 is used as a software controlled Gate A20 or user defined output. 8042 PINS The 8042 functions P17, P16 and P12 are not supported in LPC47M172.
7.25.10 External Keyboard and Mouse Interface
Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission. Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system expansion, the LPC47M172 provides four signal pins that may be used to implement this interface directly for an external keyboard and mouse. The LPC47M172 has four high-drive, open-drain output, bidirectional port pins that can be used for external serial interfaces, such as external keyboard and PS/2-type mouse interfaces. They are KCLK, KDAT, MCLK, and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0. P27 is inverted and output as KDAT. The KDAT pin is connected to P10. P23 is inverted and output as MCLK. The MCLK pin is connected to TEST1. P22 is inverted and output as MDAT. The MDAT pin is connected to P11. Note: External pull-ups may be required.
7.25.11 Keyboard Power Management
The keyboard provides support for two power-saving modes: soft powerdown mode and hard powerdown mode. In soft powerdown mode, the clock to the ALU is stopped but the timer/counter and interrupts are still active. In hard power down mode the clock to the 8042 is stopped.
7.25.12 Soft Power Down Mode
This mode is entered by executing a HALT instruction. The execution of program code is halted until either RESET is driven active or a data byte is written to the DBBIN register by a master CPU. If this mode is exited using the interrupt, and the IBF interrupt is enabled, then program execution resumes with a CALL to the interrupt routine, otherwise the next instruction is executed. If it is exited using RESET then a normal reset sequence is initiated and program execution starts from program memory location 0.
7.25.13 Hard Power Down Mode
This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the oscillator driver cell. When either RESET is driven active or a data byte is written to the DBBIN register by a master CPU, this mode will be exited (as above). However, as the oscillator cell will require an initialization time, either RESET must be held active for sufficient time to allow the oscillator to stabilize. Program execution will resume as above.
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7.25.14 Interrupts
The LPC47M172 provides the two 8042 interrupts: IBF and the Timer/Counter Overflow.
7.25.15 Memory Configurations
The LPC47M172 provides 2K of on-chip ROM and 256 bytes of on-chip RAM.
7.25.16 Register Definitions
Host I/F Data Register The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this register will read the data from the Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions for more information. Host I/F Status Register The Status register is 8 bits wide. Table 7.12 shows the contents of the Status register.
Table 7.12 - Status Register D7 UD D6 UD D5 UD D4 UD D3 C/D D2 UD D1 IBF D0 OBF
Status Register This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47M172 CPU. UD C/D Writable by LPC47M172 CPU. These bits are user-definable. (Command Data)-This bit specifies whether the input data register contains data or a command (0 = data, 1 = command). During a host data/command write operation, this bit is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0. (Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register. Setting this flag activates the LPC47M172 CPU's nIBF (MIRQ) interrupt if enabled. When the LPC47M172 CPU reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no output pin associated with this internal signal. (Output Buffer Full) - This flag is set to whenever the LPC47M172 CPU write to the output data register (DBB). When the host system reads the output data register, this bit is automatically reset.
IBF
OBF
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7.25.17 External Clock Signal
The LPC47M172 Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc POR) and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip.
7.25.18 Default Reset Conditions
The LPC47M172 has one source of hardware reset: an external reset via the nPCI_RESET pin. Refer to Table 7.13 for the effect of each type of reset on the internal registers. Table 7.13 - Keyboard and Mouse Pin/Register Reset Values DESCRIPTION KCLK KDAT MCLK MDAT Host I/F Data Reg Host I/F Status Reg Note: N/A: Not Applicable HARDWARE RESET (nPCI_RESET) Low Low Low Low N/A 00H
7.25.19 GateA20 and Keyboard Reset
The LPC47M172 provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET.
7.26
Port 92 Fast Gatea20 and Keyboard Reset
7.26.1 Port 92 Register
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Keyboard Logical Device, 0xF0) set to 1. This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.
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Table 7.14 - Keyboard Port 92 Register NAME Location Default Value Attribute Size PORT 92 92h 24h Read/Write 8 bits
BIT 7:6 5 4 3 2 1 0
PORT 92 REGISTER FUNCTION Reserved. Returns 00 when read Reserved. Returns a 1 when read Reserved. Returns a 0 when read Reserved. Returns a 0 when read Reserved. Returns a 1 when read ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high. Alternate System Reset. This read/write bit provides an alternate system reset function. This function provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual Address Mode to the Real Address Mode. This provides a faster means of reset than is provided by the Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the nALT_RST signal to pulse active (low) for a minimum of 1 s after a delay of 500 ns. Before another nALT_RST pulse can be generated, this bit must be written back to a 0.
Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND'ed together with the reset signal (KRST) from the keyboard controller to provide a software means of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller. Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6s, after a delay of a minimum of 14s. Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to Port 92. Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0). If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port 92 Register and this pulse is AND'ed with the pulse generated from the 8042. This pulse is output on pin nKBDRST and its polarity is controlled by the GPI/O polarity configuration.
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14us
~ ~ 8042
6us
P20 KRST
P92 Bit 0
KRST_GA20 configuration register Bit 2 nALT_RST Pulse Gen
14us
nKBDRST
Note: When Port 92 is disabled, writes are ignored and reads return undefined values.
~ ~
6us
Figure 7.1 - NKBDRST Circuit Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. This signal is OR'ed with the A20GATE signal from the keyboard controller and nKBDRST to control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low drives nA20M to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard controller. Upon reset, this signal is driven low. Table 7.15 - nA20M Truth Table 8042 P21 0 0 1 1 Latches On Keyboard and Mouse IRQs The implementation of the latches on the keyboard and mouse interrupts is shown following. ALT_A20 0 1 0 1 SYSTEM nA20M 0 1 1 1
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KLATCH Bit
VCC
D Q
KINT new
KINT
8042
CLR
RD 60
Figure 7.2 - Keyboard Latch
MLATCH Bit
VCC
D Q
MINT new
MINT
8042
CLR
RD 60
Figure 7.3 - Mouse Latch
The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Keyboard Logical Device at 0xF0.
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These bits are defined as follows: Bit[4]: MLATCH - Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT (default), 1=MINT is the latched 8042 MINT. Bit[3]: KLATCH - Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched KINT (default), 1=KINT is the latched 8042 KINT. See the "Configuration" section for a description of this register.
7.26.2 Keyboard and Mouse PME Generation
The LPC47M172 sets the associated PME Status bits when the following conditions occur: Keyboard Interrupt Mouse Interrupt Active Edge on Keyboard Data Signal (KDAT) Active Edge on Mouse Data Signal (MDAT) These events can cause a PME to be generated if the associated PME Wake Enable register bit and the global PME_EN bit are set. Refer to the PME Support section for more details on the PME interface logic and refer to the Runtime Register Block Runtime Registers sections for details on the PME Status and Enable registers. The keyboard interrupt and mouse interrupt PMEs can be generated when the part is powered by VCC. The keyboard data and mouse data PMEs can be generated both when the part is powered by VCC, and when the part is powered by VTR (VCC=0). When using the keyboard and mouse data signals for wakeup, it may be necessary to isolate the keyboard signals (KCLK, KDAT, MCLK, MDAT) from the 8042 prior to entering certain system sleep states. This is due to the fact that the normal operation of the 8042 can prevent the system from entering a sleep state or trigger false PME events. The LPC47M172 has a mode to select the isolation of keyboard and mouse clock and data signals by hardware when the nLPCPD signal is active and/or when the isolation bits are set by software. The mode allows the keyboard and mouse data signals to go into the wakeup logic but block the clock and data signals from the 8042. The mode may be used anytime it is necessary to isolate the 8042 keyboard and mouse signals from the 8042 before entering a system sleep state. This mode applies to ANYKEY wakeup from S3, but it does not affect wake from S1. The mode is selected by ISO_MODE bit in the Keyboard logical device configuration register 0xF0. The ISO_MODE bit is defined as follows:
Bit[7] ISO_MODE in KRST_GA20 register (0xF0)
0: Mode 1 (default) - Isolate the 8042 in hardware while the nLPCPD signal is active OR when the Keyboard and Mouse isolation bits are set by software. 1: Mode 2 - Keyboard and mouse isolation bits set by software only. (Note: the input path to the 8042 is also isolated while the nLPCPD signal is active.) The bits used to isolate the keyboard and mouse signals from the 8042 are located in Keyboard Logical Device, Register 0xF0 (KRST_GA20) and are defined below. These bits reset on VTR POR only. Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect the MDAT signal to the mouse wakeup (PME) logic. 1=block mouse clock and data signals into 8042 0= do not block mouse clock and data signals into 8042
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Bit[5]
K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the KDAT signal to the keyboard wakeup (PME) logic. 1=block keyboard clock and data signals into 8042 0= do not block keyboard clock and data signals into 8042
See the SMSC Application Note titled "Using the Enhanced Keyboard and Mouse Wakeup Feature in SMSC Super I/O Parts" for more information on isolation bits. If either of the isolation bits (M_ISO, K_SIO) is set prior to entering a sleep state where VCC goes inactive (S3-S5), then the 8042 must be reset upon exiting the sleep mode. Write 0x40 to global configuration register 0x2C to reset the 8042. The 8042 must then be taken out of reset by writing 0x00 to register 0x2C since the bit that resets the 8042 is not self-clearing. Caution: Bit 6 of configuration register 0x2C is used to put the 8042 into reset - do not set any of the other bits in register 0x2C, as this may produce undesired results. It is not necessary to reset the 8042 if the isolation bits are used for a sleep state where VCC does not go inactive (S1, S2).
Note:
It not necessary to reset the 8042 when ISO_MODE bit is set to `0', and M_ISO and K_ISO isolation bit are not set. This is because nLPCPD goes inactive high (it will remove isolation of the signals when system sleep state is exited) prior to nPCI_RESET going inactive high. The nPCI_RESET going inactive high resets the 8042.
User Note Regarding External Keyboard and Mouse:
This is an application matter resulting from the behavior of the external 8042 in the keyboard. When the external keyboard and external mouse are powered up, the KDAT and MDAT lines are driven low. This sets the KBD bit (D3) and the MOUSE bit (D4) of the PME Wake Status Register since the KDAT and MDAT signals cannot be isolated internal to the part. This causes an nIO_PME to be generated if the keyboard and/or mouse PME events are enabled. Note that the keyboard and mouse isolation modes only prevent the internal 8042 in the part from setting these status bits. Case 1: Keyboard and/or Mouse Powered by VTR The KBD and/or MOUSE status bits will be set upon a VTR POR if the keyboard and/or mouse are powered by VTR. In this case, an nIO_PME will not be generated, since the keyboard and mouse PME enable bits are reset to zero on a VTR POR. The BIOS software needs to clear these PME status bits after power-up. Case 2: Keyboard and/or Mouse Powered by VCC The KBD and/or MOUSE status bits will be set upon a VCC POR if the keyboard and/or mouse are powered by VCC. In this case, an nIO_PME will be generated if the enable bits were set for wakeup, since the keyboard and mouse PME enable bits are VTR powered. Therefore, if the keyboard and mouse are powered by VCC, the enable bits for keyboard and mouse events should be cleared prior to entering a sleep state where VCC is removed (i.e., S3) to prevent a false PME from being generated. In this case, the keyboard and mouse should only be used as PME and/or wake events from the S0 and/or S1 states. The BIOS software needs to clear these PME status bits after power-up.
7.27
General Purpose I/O
The LPC47M172 provides a set of flexible Input/Output control functions to the system designer through the 13 independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic
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I/O and can be individually enabled to generate a PME (except GP24). GPIOs must be programmed as inputs to generate a PME.
7.27.1 GPIO Pins
The Table 7.16 summarizes the GPIO functionality, including PME, Either Edge Triggered Interrupt (EETI) input capability and the power source for the buffer on the I/O pads.
Table 7.16 - GPIO Summary DEFAULT FUNCTION nCDC_DWN _ENAB GP10 GP11 GP12 GP13 GP14 GP15 ALT FUNC 1 ALT FUNC 2 PWR WELL PCI RESET VCC POR VTR POR PME/EETI
GP24 FAN_TACH1 (Note 1) FAN_TACH2 (Note 1) GP20 GP21 GP22 GP23
EETI0 EETI1 -
VTR VTR VTR VTR VTR VTR VTR VTR VTR VTRNote 1 VTRNote 1 VTRNote 1 VTRNote 1
-
-
Input Input Input Input Input Input Input Input Input Hi-Z Hi-Z Hi-Z Hi-Z
PME PME PME PME PME PME PME PME PME/EETI PME/EETI PME PME
GP16 GP17 DDCSDA_5V DDCSCL_5V DDCSDA_3V DDCSCL_3V
Note 1:
When DDC functions are selected, these pins require external pull-ups to appropriate voltages.
7.27.2 Description
Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP2. The bits in these registers reflect the value of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an output: The value written to the bit goes to the GPIO pin. Latched on read and write. All of the GPIO registers are located in the GPIO/Runtime Register logical device (see GPIO Runtime Registers section when LD_NUM=0 and Chapter 10 Runtime Register Block Runtime Registers sections when LD_NUM=1). The GPIO ports with their alternate functions and configuration state register addresses are listed in Table 7.17.
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Table 7.17 - General Purpose I/O Port Assignments DATA REGISTER BIT NO. GPIO RUNTIME REGISTER OFFSET (HEX) 15
DEFAULT FUNCTION
ALT. FUNC. 1
ALT. FUNC. 2
DATA REGISTER1
nCDC_DWN_ENAB GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 DDCSDA_5V DDCSCL_5V DDCSDA_3V DDCSCL_3V Reserved
Note 1:
GP24 FAN_TACH1 FAN_TACH2 GP20 GP21 GP22 GP23 -
EETI0 EETI1 -
GP1
GP2
0 1 2 3 4 5 6 7 0 1 2 3 4 7:5
16
The GPIO Data and Configuration Registers are located in GPIO/Runtime Register block at the offset shown from the GPIO/Runtime Register Block logical device base address.
7.27.3 GPIO Control
Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in GPIO Runtime Registers section when LD_NUM=0 and Chapter 10 Runtime Register Block Runtime Registers when LD_NUM=1. Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it can be programmed as open-drain or push-pull. Inputs and outputs can be configured as non-inverting or inverting. Bit[0] of each GPIO Configuration Register determines the port direction, bit[1] determines the signal polarity, and bit[7] determines the output driver type select. The Polarity Bit (bit 1) of the GPIO control registers control the GPIO pin when the pin is configured for the GPIO function and when the pin is configured for the alternate function for all pins, with the exception of the either edge triggered interrupts and DDC functions. The basic GPIO configuration options are summarized in Table 7.18.
Table 7.18 - GPIO Configuration Summary SELECTED FUNCTION DIRECTION BIT POLARITY BIT DESCRIPTION
GPIO
B0 0 0 1 1
B1 0 1 0 1
Pin is a non-inverted output. Pin is an inverted output. Pin is a non-inverted input. Pin is an inverted input.
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7.27.4 GPIO Operation
The operation of the GPIO ports is illustrated in Figure 7.4.
GPIO Configuration Register bit-1 (Polarity)
GPIO Configuration Register bit-0 (Input/Output)
SD-bit GPx_nIOW
D-TYPE D Q
Transparen t
0 1
Q
D
GPIO PIN
GPx_nIOR
GPIO Data Register Bit-n
Figure 7.4 - GPIO Function Illustration Note:
Figure 7.4 is for illustration purposes only and is not intended to suggest specific implementation details. When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed as an input has no effect (Table 7.19) When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been written into the GPIO data register is output to the GPIO pin. Reading from a GPIO port that is programmed as an output returns the last value written to the data register (Table 7.19). When the GPIO is programmed as an output, the pin is excluded from the PME logic.
Table 7.19 - GPIO Read/Write Behavior HOST OPERATION READ WRITE GPIO INPUT PORT LATCHED VALUE OF GPIO PIN NO EFFECT GPIO OUTPUT PORT LAST WRITE TO GPIO DATA REGISTER BIT PLACED IN GPIO DATA REGISTER
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7.27.5 GPIO PME Functionality
The LPC47M172 provides 12 GPIOs that can directly generate a PME. See the Table 7.16. The polarity bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status bit in the PME_STS2 and PME_STS3 registers. The default is the low-to-high edge. If the corresponding enable bit in the PME_EN2 and PME_EN3 registers and the PME_EN bit in the PME_EN register is set, a PME will be generated. The PME registers are runtime registers which are located at the address contained in the configuration registers 0x60 and 0x61 in Power Control/Runtime Register Block Logical Device. See GPIO Runtime Registers section when LD_NUM=0 and Chapter 10 Runtime Register Block Runtime Registers when LD_NUM=1.The PME status bits for the GPIOs are cleared on a write of `1'. The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable registers: GP10-GP17 GP20-GP23 The following PME status and enable registers for these GPIOs: PME_STS2 and PME_EN2 for GP10-GP17 PME_STS3 and PME_EN3 for GP20-GP23
7.27.6 Either Edge Triggered Interrupts
GP21 and GP22 are implemented such that they allow an PME interrupt to be generated on both a highto-low and a low-to-high edge transition, instead of one or the other as selected by the polarity bit. The either edge triggered interrupts (EETI) function as follows: If the EETI function is selected for the GPIO pin, then the bits that control input/output, polarity and open drain/push-pull have no effect on the function of the pin. However, the polarity bit does affect the value of the GP bit (i.e., register GP2, bit 2 for GP22). A PME interrupt occurs if the PME enable bit is set for the corresponding GPIO and the EETI function is selected on the GPIO. The PME status bit is set when the EETI pin transitions (on either edge) and are cleared on a write of `1'. There are also status bits for the EETIs located in the MSC_STS register, which are also cleared on a write of `1'. The MSC_STS register provides the status of all of the EETI interrupts within one register. The PME or MSC status is valid whether or not the interrupt is enabled and whether or not the EETI function is selected for the pin. The MSC_STS register is defined in GPIO Runtime Registers section when LD_NUM=0 and Chapter 10 Runtime Register Block Runtime Registers when LD_NUM=1.
7.28
PME Support
The LPC47M172 offers support for power management events (PMEs), also referred to as a System Control Interrupt (SCI) events in an ACPI system. A power management event is indicated to the chipset via the assertion of the nIO_PME signal. In the LPC47M172, the nIO_PME is asserted by active transitions on the ring indicator inputs nRI1 and nRI2, active keyboard-data edges, active mouse-data edges, programmable edges on GPIO pins and fan tachometer event. The nIO_PME pin, can be programmed to be active high or active low via the polarity bit in the nIO_PME Register. The output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the nIO_PME Register. The nIO_PME pin function defaults to active low, open-drain output. The nIO_PME Register is located at an offset 0x16 from Power Control/Runtime Register Block logical device base address. See Chapter 8 Power Control Runtime Registers and Chapter 10 Runtime Register Block Runtime Registers.
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The PME functionality is controlled by the PME status and enable registers in the Power Control/Runtime Register block, which is located at the address programmed in configuration registers 0x60 and 0x61 in Power Control/Runtime Register Logical Device. The Power Control Logical Device is selected when LD_NUM=0, and the runtime Registers Local Device is selected when LD_NUM=1. The PME Enable bit, PME_EN, globally controls PME Wake-up events. When PME_EN is inactive, the nIO_PME signal can not be asserted. When PME_EN is asserted, any wake source whose individual PME Wake Enable register bit is asserted can cause nIO_PME to become asserted. The PME Status register indicates that an enabled wake source has occurred, and if the PME_EN bit is set, asserted the nIO_PME signal. The PME Status bit is asserted by active transitions of PME wake sources. PME_Status will become asserted independent of the state of the global PME enable bit, PME_EN. The following pertains to the PME status bits for each event: The output of the status bit for each event is combined with the corresponding enable bit to set the PME status bit. The status bit for any pending events must be cleared in order to clear the PME_STS bit. Status bits are cleared on a write of `1'. For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is controlled by the polarity bit of the GPIO control register. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding PME status bits. Status bits are cleared on a write of `1'. The PME Wake registers also include status and enable bits for the fan tachometer input. The fan tachometers are not intended to be wakeup events and are only valid when VCC power is active. User Note: Clear the PME enable bits for the fan tachometers before removing VCC. See the "Keyboard and Mouse PME Generation" section for information about using the keyboard and mouse signals to generate a PME. In the LPC47M172 the nIO_PME pin can be programmed to be an open drain, active low, driver. The LPC47M172 nIO_PME pin is fully isolated from other external devices that might pull the nIO_PME signal low; i.e., the nIO_PME signal is capable of being driven high externally by another active device or pullup even when the LPC47M172 VCC is grounded, providing VTR power is active. The LPC47M172 nIO_PME driver sinks 6mA at .55V max (see section 4.2.1.1 DC Specifications, page 122, in the "PCI Local Bus Specification," revision 2.1).
7.28.1
`Wake on Specific Key' Option
The LPC47M172 has logic to detect a single keyboard scan code for wakeup (PME generation). The scan code is programmed onto the Keyboard Scan Code Register, a runtime register at offset 0x11 from the base address located in the primary base I/O address in Power Control/Runtime Register Block Logical Device. This register is powered by VTR and reset on VTR POR. The PME status bit for this event is located in the PME_STS1 register at bit 5 and the PME enable bit for this event is located in the PME_EN1 register at bit 5. See Chapter 8 Power Control Runtime Registers or Chapter 10 Runtime Register Block Runtime Registers for a definition of these registers. Data transmissions from the keyboard consist of an 11-bit serial data stream. A logic 1 is sent at an active high level. The following table shows the functions of the bits.
BIT 1 2 3 FUNCTION Start bit (always 0) Data bit 0 (least significant bit) Data bit 1
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BIT 4 5 6 7 8 9 10 11
FUNCTION Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 (most significant bit) Parity bit (odd parity) Stop Bit (always 1)
The timing for the keyboard clock and data signals are shown in the "Timing Diagrams" section. The process to find a match for the scan code stored in the Keyboard Scan Code register is as follows: Begin sampling the data at the first falling edge of the keyboard clock following a period where the clock line has been high for 115-145usec. The data at this first clock edge is the start bit. The first data bit follows the start bit (clock 2). Sample the data on each falling edge of the clock. Store the eight bits following the stop bit to compare with the scan code stored in the Keyboard Scan Code register. Sample the comparator within 100usec of the falling edge of clock 9 (for example, at clock 10). Sample the parity bit and check that the 8 data bits plus the parity bit always have an odd number of 1's (odd parity). Repeat until a match is found. If the 8 data bits match the scan code stored in the Keyboard Scan Code register and the parity is correct, then it is considered a match. When a match is found and if the stop bit is 1, set the event status bit (bit 5 of the PME_STS1 register) to `1' within 100usec of the falling edge of clock 10. The state machine will reset after 11 clocks and the process will restart. The process will continue until it is shut off by setting the SPEKEY_EN bit (see following sub-section). The state machine will reset if there is a period where the clock remains high for more than one keyboard clock period (115-145usec) in the middle of the transmission (i.e., before clock 11). This is to prevent the generation of a false PME. The SPEKEY_EN bit at bit 1 of the CLOCKI32 register at 0xF0 in Power Control/Runtime Register Block Logical Device is used to control the "wake-on-specific feature. This bit is used to turn the logic for this feature on and off. It will disable the 32kHz clock input to the logic. The logic will draw no power when disabled. The bit is defined as follows: 0= "Wake on specific key" logic is on (default) 1= "Wake on specific key" logic is off
Note:
The generation of a PME for this event is controlled by the PME enable bit (located in the PME_EN1 register at bit 5) when the logic for feature is turned on.
7.29
Fan Monitoring
The chip monitors the speed of the fans by utilizing fan tachometer input signals from fans equipped with tachometer outputs. The fan tachometer inputs are monitored by using the Fan Tachometer registers. These signals, as well as the Fan Tachometer registers, are described below.
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7.29.1 Fan Tachometer Inputs
A fan tachometer input is used to measure the speed at which a fan is rotating. The fan tachometer input is a train of square pulses with a 50% duty cycle (see Figure 7.5) that are derived from the magnetic fields generated by the rotating rotor of the fan. The speed of the fan can be determined by calculating the period of the Fan Tachometer input pulse.
Note:
All calculations are based on fans that emit 2 square pulses per revolution. Reading registers reflect a count value for one complete revolution (2 pulses). The clock source to the Fan Tachometer logic is 90kHz (nominal) derived from 14.318 MHz clock and is active when VCC power is active.
TR Fan Tachometer Input TR = Revolution Time = 60/RPM (sec) TP = Pulse Time = TR/2 (Two Pulses Per Revolution) F = 90kHz (nominal)
TP Clock Source for Counter
Figure 7.5 - Fan Tachometer Input and Clock Source
The counter is used to determine the period of the Fan Tachometer input pulse. This counter is reset on the rising edge of every other fan tachometer input pulse, and thus measures the number of clock pulses generated by the clock source for the duration of one fan tachometer revolution. Since two fan tachometer input pulses are generated per revolution of the fan rotor, the speed of the fan is easily calculated. The fan tachometer input resets the counter on every other pulse and simultaneously loads the count into its respective reading register. This value is used by the operating system to monitor the speed of the fan. The Fan Tachometer Reading registers contain the number of 11.11us periods (90kHz nominal) between full fan revolutions. Fans produce 2 pulses per revolution. These registers are updated at least once every second. This register is latched on the rising edge of every other fan tachometer pulse and when the fan count reaches FFFFh. The value FFFFh indicates that the fan is not spinning (stalled fan event), or the tachometer input is not connected to a valid signal (this could be triggered by a counter overflow) The Fan Tachometer Reading registers always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional. The Tachometer Reading registers are 16 bits, unsigned. When one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. The order is LSB first, MSB second. These registers are read only - a write to these registers has no effect. The fan tachometer reading registers are Tach1 LSB, Tach1_MSB, Tach2 LSB and Tach2 MSB. See Chapter 8 Power Control Runtime Registers and Chapter 10 Runtime Register Block Runtime Registers.
7.29.2 Detection of a Stalled Fan
The fan failure bit in the interrupt status register is set in the event of a stalled fan. Note: the fan tachometer reading register, which holds the count value, does not roll over - it stays at FFFFh in the
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event of a stalled fan. The internal count register does rollover, however, and continuously counts to FFFFh as long as the fan is stalled. In the event the counter reaches FFFFh, the PME status bit is set and the count value is latched into the register. The second subsequent fan tach pulse resets the counter but does not latch the count value. Every second fan tach pulse latches the fan count value into the fan tachometer register except for this special case. The fan stalled event can generate a PME if properly enabled. Note the fan stalled PME is not a wakeup event, and it can indicate a fan stalled event if VCC is active.
7.30
Hard Drive and Power LED Logic
7.30.1 Hard Drive Front Panel LED (Red)
Table 7.20 - Hard Drive Front Panel Pins NAME BUFFER POWER WELL VCC VCC DESCRIPTION
nSCSI nHD_LED nSECONDARY_HD nPRIMARY_HD
Notes:
ISPU_400 OD12 ISPU_400 ISPU_400
VCC VCC
SCSI Drive Active Input Hard Drive Front Panel LED Open-Drain Output IDE Secondary Drive Active Input IDE Primary Drive Active Input
The nHD_LED requires external pull-up to VCC. ISPU_400 is defined as: Input with Schmitt Trigger, 400 mV hysteresis, with 30uA internal pull-up. The nHD_LED pin is a logical AND of the inputs nPRIMARY_HD, nSECONDARY_HD and nSCSI used to drive a single color LED. The inputs are internally pulled to VCC. See table below for state definitions. The nHD_LED pin is used at the system's front panel header to drive the hard drive activity LED. Note that external LEDs should be driven such that the voltage at the nHD_LED pin does not exceed 5V. The output is open-drain and should be externally pulled to VCC through a resistor.
Table 7.21 - nHD_LED Truth Table NPRIMARY_HD 0 X X 1 INPUTS NSECONDARY_HD X 0 X 1 NSCSI X X 0 1 OUTPUT nHD_LED 0 0 0 Hi-Z NOTES LED On LED On LED On LED Off
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VCC
220 ohms
SMSC I/O
RED
nHD_LED
Figure 7.6 - NHD_LED Circuit
7.30.2 Yellow and Green Power LED Pins
Table 7.22 - LED Pins NAME BUFFER POWER WELL VTR DESCRIPTION
GRN_LED YLW_LED nSLP_S5
OD24 OD24 I
VTR VTR
Green Power LED Open-Drain Output Yellow Power LED Open-Drain Output Input from South Bridge for Transitioning to the S5 Power State
Note:
The LEDs require external pull-up to VTR. The green and yellow LED outputs are controlled by the LED register accessible via the LPC bus. The GRN_YLW bit controls which output is asserted. In addition, the SDY_BLK bit indicates whether the selected LED is steady or blinking. The LED register is defined in Chapter 10 Runtime Register Block Runtime Registers. These LED outputs are also controlled by the nSLP_S5 sleep input pin. The functionality is shown in the table below. The green and yellow LED outputs are powered by VTR.
Table 7.23 - LED Truth Table nSLP_S5 0 0 0 0 1 1 INPUTS GRN_YLW Bit 0 0 1 1 0 0 OUTPUTS SDY_BLK Bit 0 1 0 1 0 1 GRN_LED 0 0 0 0 0 0 YLW_LED 0 0 0 0 0.67 Hz Hi-Z
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nSLP_S5 1 1 Notes:
INPUTS GRN_YLW Bit 1 1
OUTPUTS SDY_BLK Bit 0 1 GRN_LED 0.67 Hz Hi-Z*** YLW_LED 0 0
*** Default state The LED is ON in the Hi-Z state. The LED is blinking at 0.67 Hz in the 0.67 Hz state. The 32.768 kHz clock input is used to control the blink rate and duty cycle of the LEDs. The blink rate is 0.67Hz, and the duty cycle is 39.6%. This corresponds to a LED low output of exactly 0.90625 seconds (depending on the accuracy of the 32.768 kHz clock). YLW_LED and GRN_LED require external pull-ups to power the LEDs. A value of 220ohms to VTR is recommended. These are open drain active high outputs. When the LEDs are off, the open drain output is sinking the current from VTR through the 220ohm resistor to ground. When the LEDs are on, they are powered through the 220ohm resistor. The following figure shows the recommended external LED circuit.
VTR
220 ohms
220 ohms
SMSC I/O
GRN_LED YLW_LED
Green
Yellow
Figure 7.7 - YLW_LED/GRN_LED Circuit
7.31
Power Generation (5V)
7.31.1 Reference Pins
Table 7.24 - Reference Generation Pins NAME BUFFER MAX OUT CURRENT 3.3mA 3.3mA POWER WELL VCC VTR DESCRIPTION
REF5V REF5V_STBY
AO AO
5V Reference Output Highest System Standby Voltage
OAN: Analog Output, 5V level. See DC characteristics see the "Electrical Characteristics" section.
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7.31.2 5V Main Reference Generation
REF5V is used to help power-up various system components' 5V tolerant buffers. This signal is used to guarantee there are no power sequencing requirements at each particular system component. REF5V is powered by VCC when VCC5V < VCC. Upon motherboard power-up, REF5V is an analog output signal that tracks either VCC or VCC5V (through an external pull-up resistor), whichever is greater in amplitude. REF5V becomes a high impedance input while tracking the VCC power supply.
Table 7.25 - REF5V MAIN SUPPLY VCC5V < VCC VCC5V > VCC REF5V VCC Hi-Z
Backdrive Protection VCC (3.3V)
VCC5V
1k
REF5V
SMSC I/O
Figure 7.8 - REF5V Circuit Note:
The maximum voltage drop across the diode is 350mV.
7.31.3 5V Standby Reference Generation
REF5V_STBY is generated in the same manner as REF5V, but in reference to V_5P0_STBY and VTR instead. REF5V_STBY serves the same purpose as REF5V, but tracks different power supplies. REF5V_STBY is an analog output signal that tracks either VTR or V_5P0_STBY, whichever is greater in amplitude. Upon motherboard power-up, REF5V_STBY is an analog output signal that tracks either VTR or V_5P0_STBY (through an external pull-up resistor), whichever is greater in amplitude. REF5V_STBY becomes a high impedance input while tracking the V_5P0_STBY power supply. REF5V_STBY is powered by VTR when VTR > V_5P0_STBY.
Table 7.26 - REF5V_STBY STANDBY SUPPLY V_5P0_STBY < VTR V_5P0_STBY > VTR REF5V_STBY VTR Hi-Z
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Backdrive Protection
VTR (3.3V)
V_5P0_STBY
1k
REF5V_STBY
SMSC I/O
Figure 7.9 - REF5V_STBY Note:
The maximum voltage drop across the diode is 350mV.
7.31.4 Reference Timings
See Figure 13.25 to Figure 13.28 in the "Timing Diagrams" section.
7.32
IDE Reset Output Pin
nIDE_RST is an open drain buffered copy of nPCI_RESET. This signal requires an external 1kohm pull-up to VCC5V. This signal will be low when VCC5V=0 since it is externally pulled up to VCC5V.
Table 7.27 - nIDE_RSTDRV Pin NAME BUFFER POWER WELL VCC DESCRIPTION
nIDE_RSTDRV
OD8
IDE Reset Output
Table 7.28 - nIDE_RSTDRV Truth Table nPCI_RESET (Input) 0 1 nIDE_RSTDRV (Output) 0 Hi-Z
See Table 13.1 for nIDE_RSTDRV timing.
7.33
PCI Reset Output Pins
The nPCIRST_OUT is 3.3V buffered copy of nPCI_RESET. The nPCIRST_OUT2 is 3.3V buffered copy of nPCI_RESET. The nPCIRST_OUT and nPCIRST_OUT2 signals will be low when VCC=0.
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Table 7.29 - nPCIRST_OUT Pins NAME BUFFER POWER WELL VTR VTR DESCRIPTION
nPCIRST_OUT nPCIRST_OUT2
OP14 OP14
Buffered PCI Reset Output Buffered PCI Reset Output
Table 7.30 - nPCIRST_OUT and nPCIRST_OUT2 Truth Table INPUT nPCI_RESET 0 1 OUTPUTS nPCIRST_OUT nPCIRST_OUT2 0 0 1 1
See Table 13.2 for nPCI_RSTOUT and nPCI_RSTOUT2 timings.
7.34
Voltage Translation Circuit
Table 7.31 - Voltage Translation DDC Pins NAME BUFFER POWER WELL VTR DESCRIPTION
DDCSDA_5V/ GP20 DDCSCL_5V/ GP21 DDCSDA_3V/ GP22 DDCSCL_3V/ GP23
Note:
IO_SW IO_SW IO_SW IO_SW
VTR VTR VTR
5V DDC Data IOD/ GPIO (Note) 5V DDC Clock IOD/ GPIO (Note ) 3.3V DDC Data IOD/ GPIO (Note) 3.3V DDC Clock IOD/ GPIO (Note)
The DDC_5V signals require external pull-up to VCC5V. The DDC_3V signals require external pull-up to VCC. If DDC functions are selected on the pins, the pins will tri-state when VCC is removed. The VGA DDC voltage translation circuitry is used in conjunction with integrated VGA chipsets. Since the chipset operates at 3.3V signal levels and the VGA signals are specified at 5V signal levels, on-board voltage translation is needed for the DDC signals. This is a non-inverting translation. See the Table 7.32 and Table 7.33 for further details on the logic. The DDC data pins and the DDC clock pins function as inputs shorted together through the isolation resistor. The DDC signals require external pull-up resistors on LPC47M172. See the "Pins That Require External Resistors" section for resistor values. See Figure 7.10 for recommended schematic implementation. Note the switch is always on after the DDC functions are selected on the GPIO pins. That is, the switch is controlled by the GPIO alternate function select bits. Once the DDC functions are selected, the switch is closed and remains closed when VCC is removed. The current flow is controlled by the external signals on the DDC pins. See the tables below for the current flow across the switch based on the voltage levels on the pins. The switch provides a 25ohm resistance to ground. This circuit requires ESD protection external to the chip to protect the device from hot-plugging on the VGA connector. See the "Electrical Characteristics" section for current and voltage requirements. Due to the multiplexing with GPIO pins, these pins are powered by VTR. (Without the multiplexing requirement, these pins could be powered by VCC).
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Note:
If any of the Alternate Function Select bits in GP20 to GP23 registers are set for DDC function, the DDC functions will be selected on all four GP20 to GP23 pins. However, it is recommended that the DDC functions be selected via the Alternate Function Select bits in all of the GP20 to GP23 registers when using the DDC functions. The GP20 to GP23 registers are defined in Chapter 8 Power Control Runtime Registers and Chapter 10 Runtime Register Block Runtime Registers.
Table 7.32 - VGA DDCSDA Voltage Translation Logic
DDC VS. GPIO ALTERNATE FUNCTION SELECT BIT/S GPIO/EETI/Reserved
DDCSDA_3V
DDCSDA_5V
CURRENT ACROSS THE SWITCH
Don't Care 0V 3.6V (max)
Don't Care 0V 5.5V (max)
DDC (DEFAULT) DDC (DEFAULT)
No Current flow (0 mA) Current flows from DDCSDA_5V or DDCSDA_3V No Current flow (0 mA)
Table 7.33 - VGA DDCSCL Voltage Translation Logic DDC Vs. GPIO ALTERNATE FUNCTION SELECT BIT/S GPIO/EETI/Reserved
DDCSCL_3V
DDCSCL_5V Don't Care 0V 5.5V (max)
CURRENT ACROSS THE SWITCH
Don't Care 0V 3.6V (max)
DDC (DEFAULT) DDC (DEFAULT)
No Current flow (0 mA) Current flows from DDCSCL_5V or DDCSCL_3V No Current flow (0 mA)
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VCC
LPC47M172
25ohm Max
VCC5V
4.7k
4.7k
2.2k
2.2k
DDCSDA_3V
DDCSDA_5V
MCH
DDCSCL_3V
SEE NOTE
25ohm Max EN 6.2V 6.2V
DDCSCL_5V
VGA Connector
GPIO Alternate Function Select bit
NOTE: The switch is implemented as an n-channel switch that will not pass a full voltage swing. It provides a current path to ground. The board designer should treat each signal pair to the switch as a separate bus with a resistance in the path. The maximum resistance of the switch between any bus to any other bus is 25ohms (when the switch is on). When the switch is off the impedance is Hi-Z and the current is zero. The design requires pull-ups on each of the busses shown above. It is recommended that the pullups be selected so that the total maximum current on both busses does not exceed 2mA to limit the voltage drop across the switch.
Figure 7.10 - VGA DDC Voltage Translation Circuit
7.35
SMBus Isolation Circuitry
Table 7.34 - SMBus Isolation Pins NAME BUFFER POWER WELL VTR VTR VTR VTR DESCRIPTION
SMB_CLK_M SMB_DAT_M SMB_CLK_R SMB_DAT_R
IO_SW IO_SW IO_SW IO_SW
Main Well SMBus Clock Main Well SMBus Data Resume Well SMBus Clock Resume Well SMBus Data
The SMBus Isolation circuitry is used to isolate the main SMBus signals from the resume SMBus signals during power down modes. The SMB data pins and the SMB clock pins function as inputs shorted together through the isolation resistor when the switch is closed. The SMBus signals require external pull-up resistors on LPC47M172. See Figure 7.11 for recommended schematic implementation. The switch is controlled by the PWRGD_PS signal. The switch is closed as long as PWRGD_PS is `1'. The current flow is controlled by the external signals on the SMB pins. See Table 7.35 and Table 7.36 for the current flow across the switch based on the voltage levels on the pins. The switch provides a 25ohm resistance to ground. These pins are powered by VTR.
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Table 7.35 - SMB_CLK Isolation Logic PWRGD_PS 0 SMB_CLK_M Don't Care SMB_CLK_R Don't Care CURRENT ACROSS THE SWITCH No Current flow (0 mA) Current flows from SMB_CLK_R or SMB_CLK_M No Current flow (0 mA)
1 1
0V 3.6V (max)
0V 3.6V (max)
Table 7.36 - SMB_DAT Isolation Logic PWRGD_PS SMB_DAT_M SMB_DAT_R CURRENT DIRECTION ACROSS THE SWITCH No Current flow (0 mA) Current flows from SMB_DAT_R or SMB_DAT_M No Current flow (0 mA)
0 1 1
Don't Care 0V 3.6V (max)
Don't Care 0V 3.6V (max)
VCC
LPC47M172
25ohm Max
VTR
2.7k
2.7k
2.7k
2.7k
ICH, CNR, DIMMS, CLK GEN
SMB_CLK_M
SMB_CLK_R
SEE NOTE
SMB_DAT_M PWRGD_PS
25ohm Max EN
ICH, PCI
SMB_DAT_R
NOTE: The switch is implemented as an n-channel switch that will not pass a full voltage swing. It provides a current path to ground. The board designer should treat each signal pair to the switch as a separate bus with a resistance in the path. The maximum resistance of the switch between any bus to any other bus is 25ohms (when the switch is on). When the switch is off the impedance is Hi-Z and the current is zero. The design requires pull-ups on each of the busses shown above. It is recommended that the pullups be selected so that the total maximum current on both busses does not exceed 2mA to limit the voltage drop across the switch.
Figure 7.11 - SMBUS Isolation Circuit
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7.36
PS_ON Logic
Table 7.37 - nPS_ON, nCPU_PRESENT and nSLP_S3 Pins NAME BUFFER POWER WELL VTR DESCRIPTION
nPS_ON nCPU_PRESENT nSLP_S3
OD8 ISPU_400 I
VTR VTR
Power Supply Turn-ON Open Drain Output CPU Present Input from Processor S3 Power State Input from South Bridge
The nPS_ON is a function of nSLP_S3 and nCPU_PRESENT according to the truth table below. The nCPU_PRESENT is the signal from the processor that tells the system whether or not a processor has been plugged in. The nCPU_PRESENT will be pulled to VTR through a 30uA resistor inside the chip. The nPS_ON is used as the power down signal for the power supply. Since nPS_ON is an open drain output, it may need to be pulled through a 1kohm resistor to V_5P0_STBY external to the chip if such a pull-up is not provided on the power supply. The power supply turn-on circuit behaves according to the table below.
Table 7.38 - nPS_ON Truth Table INPUTS NCPU_PRESENT 0 0 1 1 NSLP_S3 0 1 0 1 OUTPUT nPS_ON Hi-Z 0 Hi-Z Hi-Z
See Table 13.3 for nPS_ON timing.
7.37
PWRGD_3V Logic
Table 7.39 - PWRGD_3V, nFPRST and PWRGD_PS Pins NAME BUFFER POWER WELL VTR VTR DESCRIPTION
nFPRST PWRGD_PS PWRGD_3V
ISPU_400 ISPU_400 O8
VTR
Reset Input from Front Panel Power Good Input from Power Supply Power Good Output
The PWRGD_3V is an AND function of PWRGD_PS and nFPRST. The inputs, PWRGD_PS and nFPRST have hysteresis and are internally pulled to VTR through a 30uA resistor. The nFPRST is debounced internally. nFPRST has internal debounce circuitry that is valid on both edges for at least 16ms before the output is changed. The 32.768kHz is used to meet the timing requirement. See Figure 7.14 for nFPRST debounce timing.
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Note:
The actual minimum debounce time is 15.8msec
See Table 13.5 for PWRGD_3V timing.
Table 7.40 - PWRGD_3V Truth Table INPUTS nFPRST 0 0 1 1 PWRGD_PS 0 1 0 1 OUTPUT PWRGD_3V 0 0 0 1
The following figure shows the discrete implementation for the creation of the PWRGD_3V signal on the motherboard.
nFPRST
3.3kohm
PWRGD_3V
1uF
PWRGD_PS
Figure 7.12 - PWRGD_3V Circuit, Discrete Implementation
(SHOWING NFPRST INPUT DEBOUNCE CIRCUITRY)
The following figure represents the integration of the logic into the LPC47M172.
nFPRST
Debounce Circuitry
SMSC I/O
PWRGD_PS
PWRGD_3V
Figure 7.13 - PWRGD_3V Circuit in LPC47M172
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Press nFPRST (before debounce) 15.8msec min
Release
15.8msec min
Internal nFPRST (after debounce) The next nFPRST press will be detected starting here
Figure 7.14 - NFPRST Timing
7.38
SCK_BJT_GATE Output
Table 7.41 - SCK_BJT_GATE Pin NAME BUFFER POWER WELL VTR DESCRIPTION
SCK_BJT_GATE
Note:
OD8
Open-Drain Gate Output for the SCK_BJT_GATE in S3
The SCK_BJT_GATE requires external pull-up to V_5P0_STBY. The SCK_BJT_GATE pin is an open drain output that provides the gate signal for SCK_BJT in the S3 power state. This circuit is used for glitch protection on the SCK line when moving in to and out of the S3 power state. This signal is only required for designs utilizing Rambus memory. This output functions according to the table below. See the figure below for the circuit implementation.
Table 7.42 - SCK_BJT_GATE Truth Table PWRGD_3V (INPUT) 0 SCK_BJT_GATE (OUTPUT) Hi-Z
1
0
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MCH
RMB_SCK
V_5P0_STBY 1k
SMSC I/O
SCK_BJT_GATE
Figure 7.15 - SCK_BJT_Gate Circuit
See Table 13.4 for SCK_BJT_GATE timing.
7.39
Backfeed Cut and Latched Backfeed Cut Circuitry
Table 7.43 - nBACKFEED_CUT and LATCHED_BF_CUT Pins Name Buffer Power Well Description
nBACKFEED_CUT LATCHED_BF_CUT
Note:
OD8 OP14
VTR VTR
Open-Drain Output used for STR Circuitry Latched Backfeed Cut Output for STR Circuitry
The nBACKFEED_CUT requires an external pull-up to V_5P0_STBY. nBACKFEED_CUT is a signal required by the S3 power state circuitry and is powered by the VTR supply. It is a function PWRGD_PS and nSLP_S3 according to the table below. nBACKFEED_CUT is used to switch between the main voltage regulator and the suspend voltage regulator for various sub-systems when the system is transitioning into the S3 power state.
Table 7.44 - nBACKFEED_CUT Truth Table INPUTS PWRGD_PS 0 0 1 1 NSLP_S3 0 1 0 1 OUTPUT nBACKFEED_CUT Hi-Z Hi-Z Hi-Z 0
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+5VTR 1k
nBACKFEED_CUT
+12 1k
PWRGD_PS
BACKFEED_CUT
nSLP_S3
SMSC I/O
1k
nSLP_S5
LATCHED_BF_CUT
+12
470 ohms +5VTR 1k
470 ohms
Figure 7.16 - Backfeed Cut and Latched Backfeed Cut Circuit
The LATCHED_BF_CUT is generated from nBACKFEED_CUT and nSLP_S5. It is powered by VTR.
Table 7.45 - LATCHED_BF_CUT Truth Table INPUTS NBACKFEED_CUT (INTERNAL SIGNAL) 0 0 1 0 to 1 (rising edge) `1' and no rising edge Note: OUTPUT NSLP_S5 LATCHED_BF_CUT
0 1 0 1 1
0 0 0 1 No Change (Note)
This is the condition when nBACKFEED_CUT stays high and nSLP_S5 goes low and then high again (see Figure 7.19).
APPLICATION NOTE: The figure below shows the power up sequence. The nBACKFEED_CUT signal follows the power rail up to its final value. The LATCHED_BF_CUT signal stays low and never turns on. The nSLP_S5 goes to its high value when the power rails have stabilized, approximately 25msec after power on. nBACKEED_CUT is pulled low a period t1 after nSLP_S5 goes high. The period t1 can be as short as 1msec. Typical measured values are
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approximately 200msec. The t1 and t2 values are guaranteed by the inherent design of the system and are not controlled by the LPC47M172.
V_5P0_STBY nSLP_S3 PWRGD_PS
t2
nBACKFEED_CUT nSLP_S5
LATCHED_BF_CUT
t1
Figure 7.17 - Latched Backfeed Cut Power Up Sequence Table 7.46 - Latched Backfeed Cut Power Up Sequence Timing NAME t1 DESCRIPTION nSLP_S5 inactive to nBACKFEED_CUT active nSLP_S5 inactive after power rails have stabilized MIN 1 TYP 200 MAX UNITS msec
t2
Note:
25
msec
Periods t1 and t2 should be guaranteed by the inherent design of the system. These timings are not controlled by the LPC47M172. There are two possible timing sequences following the power up signal sequencing. The first possible sequence is with nSLP_S5 staying high and nBACKFEED_CUT transitioning from low to high, remaining high for an undetermined period and then going back to low. At this point, the system returns to the end of the power-up sequence. During these nBACKFEED_CUT transitions, the propagation delays, rise and fall times for LATCHED_BF_CUT are as described in the figure below. The first sequence can start at the end of the power-up sequence at any time.
nSLP_S3 PWRGD_PS nSLP_S5 nBACKFEED_CUT LATCHED_BF_CUT Tpropr Tr
Figure 7.18 - Latched Backfeed Cut Sequence 1
nSLP_S5 = 1
Tpropf Tf
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The second possible sequence, shown in the figure below, is a normal powerdown sequence. The nBACKFEED_CUT signal goes from low to high when nSLP_S3 goes low, and nSLP_S5 goes from high to low 30usec to 65usec (t3) later. The LATCHED_BF_CUT signal goes high when nBACKFEED_CUT LATCHED_BF_CUT returns to low when nSLP_S5 goes low. goes high and then
The nBACKFEED_CUT stays high and nSLP_S5 stays low for an indeterminate time and then nSLP_S5 will go high. A minimum of 1msec (t4) later, nBACKFEED_CUT will go low and the system returns to the end of the power-up sequence when nSLP_S3 and PWRGD_3V goes high. Typical measured values of t4 are approximately 250msec. During all transitions, the propagation delays, rise and fall times and power regulation times for LATCHED_BF_CUT are as described in Figure 7.19. The first sequence can start at the end of this power-up sequence at any time.
nSLP_S3 PWRGD_PS t3 nBACKFEED_CUT nSLP_S5
Tpropr Tpropf
t4
LATCHED_BF_CUT
Tr
Tf
Figure 7.19 - Latched Backfeed Cut Sequence 2 Table 7.47 - Latched Backfeed Cut Sequence 1 and 2 Timing NAME Tr DESCRIPTION MIN LATCHED_BF_CUT rise time. Measured from 10% to 90%. LATCHED_BF_CUT fall time. Measured from 90% to 10%. LATCHED_BF_CUT high to low propagation delay. Measured from nBACKFEED_CUT/nSLP_S5 threshold to 90% of LATCHED_BF_CUT LATCHED_BF_CUT low to high propagation delay. Measured from nBACKFEED_CUT/nSLP_S5 threshold to 10% of LATCHED_BF_CUT Output Capacitance Load Capacitance 30 nBACKFEED_CUT inactive to nSLP_S5 active 1 nSLP_S5 inactive to nBACKFEED_CUT active TYP MAX
1 1 50
UNITS us
Tf Tpropf
us ns
Tpropr
50
ns
CO CL t3 t4
25 50 60 250
pF pF us ms
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The following figure shows a flowchart of the logic.
Start of Suspend Power Up Sequence
nBACKFEED_CUT = 1? nBACKFEED_CUT = 0 nSLP_S5 = 0 LATCHED_BF_CUT = 0 No No Yes LATCHED_BF_CUT = 1 (After Tpropr)
nBACKFEED_CUT = 1? nSLP_S5 = 0? Yes No nBACKFEED_CUT = 0? Power Rails Stabilized? (Period T2) (Verified by ICH) No Yes
LATCHED_BF_CUT = 0 (After Tpropf) (This is end of T3)
No
Yes LATCHED_BF_CUT = 0 (After Tpropf) nSLP_S5 = 1? Yes
Yes nSLP_S5 = 1 (Controlled by ICH)
No
Period T4
No
nBACKFEED_CUT = 0? (Period T1) Yes End of Power Up Sequence Main Power Active
nBACKFEED_CUT = 0 (Controlled by nSLP_S3 and PWRGD_PS)
Figure 7.20 - Latched Backfeed Cut Flowchart
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7.40
Resume Reset Logic
Table 7.48 - nRSMRST Pin NAME BUFFER POWER WELL VTR DESCRIPTION
nRSMRST V_5P0_STBY
O8 PWR
Resume Reset Output 5V Standby
The nRSMRST signal is the reset output for the ICH resume well. This signal is used as a power on reset signal as well as a brown-out sensor for the ICH. The rising edge of nRSMRST is a delayed 3.3V buffered copy of V_5P0_STBY. This delay, tRESET_DELAY, nominally 32ms, starts when V_5P0_STBY hits the trip point, VTRIP. Note the nRSMRST will be inactive high after the tRESET_DELAY only if VTR (3.3V) is present. Otherwise, nRSMRST will be active low beyond the tRESET_DELAY - until VTR (3.3V) goes active. On the falling edge there is minimal delay, tRESET_FALL. Note that VTRIP shown in Figure 26 has a VTRIP_MIN and a VTRIP_MAX. See Table below for timing and voltage parameters. Note that no internal clock is available during nRSMRST generation, so an internally generated delay is required. The requirements are loose enough that an onboard RC delay is permissible. This delay is only required at V_5P0_STBY power on and brown-out recovery. See Table 13.7 for nRSMRST timing.
7.41
CNR Logic
Table 7.49 - CNR Pins NAME TYPE POWER WELL VTR VTR DESCRIPTION
nAUD_LNK_RST nCDC_DWN_ENAB/ GP24 nCDC_DWN_RST
I IO12 O12
VTR
Audio Link Reset Input CODEC Down Enable Input/GPIO CODEC Down Reset Output
The CNR CODEC Down Enable Circuitry is used in conjunction with soft audio and motherboards with a CNR slot. This feature allows the Basic Input / Output System (BIOS) to enable an audio CNR board. See figure and table below for implementation and definition of the input and output states. Note that these signals are required in all sleep states. The CNR circuitry is powered from VTR. The nCDC_DWN_ENAB pin also functions as a GPIO. This allows BIOS to drive the pin to a known state if the motherboard requires it. Note that nCDC_DWN_RST still follows the nCDC_DWN_ENAB pin even when it is functioning as a GPIO output. The nCDC_DWN_ENAB/GP24 pin functions as follows: When the nCDC_DWN_ENAB function is selected on GP24, it will be an input to the CNR logic. The polarity bit will not affect the input. If GP24 is programmed as GPIO output the GP data bit will control nCDC_DWN_ENAB input to the CNR logic. The data bit will also be reflected on the GP24 pin as an output under both VCC and VTR power. The polarity bit will affect the output and input to the CNR logic. The output type select bit will also affect the GP24 pin. If GP24 is programmed as GPIO input, it will not affect the nCDC_DWN_ENAB input into the CNR logic. It will function as a normal GPIO input and can be used as a PME event.
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Table 7.50 - CNR Logic Truth Table INPUTS NCDC_DWN_ENAB NAUD_LNK_RST (NOTE) 0 0 0 1 1 0 1 1 Note: OUTPUT nCDC_DWN_RST
0 0 1 0
If GP24 is programmed as GPIO output the GP data bit will also control nCDC_DWN_ENAB input to the CNR logic. This follows the boolean equation:
(nAUD_LNK_RST)x( nCDC_DWN_ENAB )=nCDC_DWN_RST
SMSC I/O
nAUD_LNK_RST
nCDC_DWN_ENAB
nCDC_DWN_RST
10k
Powered by VTR (3.3V)
Figure 7.21 - CNR Circuit
See Table 13.6 for CNR timing.
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Chapter 8
Power Control Runtime Registers
Table 8.1 shows the runtime registers summary in the Power Control logical Device. Table 8.2 shows the runtime registers description in the Power Control logical device. These runtime registers can only be accessed when LD_NUM bit in the TEST 7 configuration register is `0' (see Table 11.3). The register offsets are from the base address programmed in the Power Control logical device.
Table 8.1 - Power Control Runtime Registers Summary, LD_NUM Bit = 0 REGISTER OFFSET (hex) 00 TYPE PCI Reset VCC POR VTR POR SOFT RESET REGISTER
R/W R R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R R R R R/W R/W R/W R R R/W R/W R R
0x01 0xFF 0xFF -
0x01 0xFF 0xFF -
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x80 0x00 -
-
PME_STS Reserved - reads return 0 PME_EN Reserved - reads return 0 PME_STS3 PME_STS2 PME_STS1 Reserved - reads return 0 PME_EN3 PME_EN2 PME_EN1 Reserved - reads return 0 LED Keyboard Scan Code Tach1 LSB Tach1 MSB Tach2 LSB Tach2 MSB nIO_PME Register MSC_STS Force Disk Change Floppy Data Rate Select Shadow UART1 FIFO Control Shadow Interrupt Generating Register 1 Interrupt Generating Register 2 UART2 FIFO Control Shadow Reserved - reads return 0
01 - 03 04 05 - 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E-1F
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Table 8.2 - Power Control Runtime Registers Description, LD_NUM Bit = 0 NAME REG OFFSET (Type) 0x00 DESCRIPTION
PME_STS Default = 0x00 on VTR POR
(R/W)
N/A PME_EN Default = 0x00 on VTR POR N/A PME_STS3 Default = 0x00 on VTR POR
0x01 - 0x03 (R) 0x04 (R/W)
Bit[0] PME_Status = 0 (default) = 1 Set when LPC47M172 would normally assert the nIO_PME signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a "1" to PME_Status will clear it and cause the LPC47M172 to stop asserting nIO_PME, in enabled. Writing a "0" to PME_Status has no effect. Bits[7:0] Reserved - reads return 0 Bit[0] PME_En = 0 nIO_PME signal assertion is disabled (default) = 1 Enables LPC47M172 to assert nIO_PME signal Bit[7:1] Reserved PME_En is not affected by Vcc POR, SOFT RESET or HARD RESET Bits[7:0] Reserved - reads return 0 PME Wake Status Register 3 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP23 Bits[7:4] Reserved The PME Wake Status register is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. PME Wake Status Register 2 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect.
0x05 - 0x07 (R) 0x08 (R/W)
PME_STS2 Default = 0x00 on VTR POR
0x09 (R/W)
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NAME
PME_STS1 Default = 0x00 on VTR POR
REG OFFSET (Type) 0x0A
DESCRIPTION
(R/W)
N/A PME_EN3 Default = 0x00 on VTR POR
0x0B (R) 0x0C (R/W)
PME Wake Status Register 1 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] Reserved (Note 1) Bit[1] RI2 Bit[2] RI1 Bit[3] KBD Bit[4] MOUSE Bit[5] SPEKEY (Wake on specific key) Bit[6] FAN_TACH1 (Note) Bit[7] FAN_TACH2 (Note) The PME Wake Status register is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. Note: When the GP1x/FAN_TACHx pin is configured as a GPIO (GPIO control register bit 2 = 0), the associated PME status bit will never be set. When the pin is configured for the tachometer function (GPIO control register bit 2 = 1) and then the function is switched to the GPIO function, the associated PME status bit will be cleared. Bits[7:0] Reserved - reads return 0 PME Wake Status Register 3 This register is used to enable individual LPC47M172 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP23 Bits[7:4] Reserved The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET.
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NAME
PME_EN2 Default = 0x00 on VTR POR
REG OFFSET (Type) 0x0D
DESCRIPTION
(R/W)
PME_EN1 Default = 0x00 on VTR POR
0x0E (R/W)
N/A LED Default = 0x03 on VTR POR
0x0F (R) 0x10 (R/W)
PME Wake Enable Register 2 This register is used to enable individual LPC47M172 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET. PME Wake Enable Register 1 This register is used to enable individual PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] Reserved (Note 1) Bit[1] RI2 Bit[2] RI1 Bit[3] KBD Bit[4] MOUSE Bit[5] SPEKEY (Wake on specific key) Bit[6] FAN_TACH1 Bit[7] FAN_TACH2 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET. Bits[7:0] Reserved - reads return 0 LED Register Bit[0] GRN_YLW 0 = Select YLW_LED if nSLP_S5 if high 1 = Select GRN_LED if nSLP_S5 is high Bit[1] SDY_BLK 0 = Blink at 0.67 Hz with 39.6% duty cycle (0.59375 sec high, 0.90625 low) if nSLP_S5 is high 1 = Steady if nSLP_S5 is high Bit[7:2] Reserved
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NAME
Keyboard Scan Code Default = 0x00 on VTR POR Tach1 LSB Default = 0x00 on VTR POR Tach1 MSB Default = 0x00 on VTR POR Tach2 LSB Default = 0x00 on VTR POR Tach2 MSB Default = 0x00 on VTR POR nIO_PME Register Default = 0x80 on VTR POR MSC_STS Default = 0x00 on VTR POR
REG OFFSET (Type) 0x11
DESCRIPTION
(R/W)
0x12 (R) 0x13 (R) 0x14 (R) 0x15 (R) 0x16 (R/W)
0x17 (R/W)
Keyboard Scan Code Bit[0] LSB of Scan Code ... ... ... Bit[7] MSB of Scan Code This register is least significant 8-bit of the 16-bit Fan Tachometer 1 reading. Bit[0] FAN_TACH1 Reading Bit 0 ... Bit[7] FAN_TACH1 Reading Bit 7 This register is most significant 8-bit of the 16-bit Fan Tachometer 1 reading. Bit[0] FAN_TACH1 Reading Bit 8 ... Bit[7] FAN_TACH1 Reading Bit 15 This register is least significant 8-bit of the 16-bit Fan Tachometer 2 reading. Bit[0] FAN_TACH2 Reading Bit 0 ... Bit[7] FAN_TACH2 Reading Bit 7 This register is most significant 8-bit of the 16-bit Fan Tachometer 2 reading. Bit[0] FAN_TACH2 Reading Bit 8 ... Bit[7] FAN_TACH2 Reading Bit 15 Bit[0] Reserved Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain (default) 0=Push Pull Miscellaneous Status Register Bits[1:0] can be cleared by writing a 1 to their position (writing a 0 has no effect). Bit[0] Either Edge Triggered Interrupt Input 0 Status. This bit is set when an edge occurs on the GP21 pin. Bit[1] Either Edge Triggered Interrupt Input 1 Status. This bit is set when an edge occurs on the GP22 pin. Bit[7:2] Reserved. This bit always returns zero.
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NAME
Force Disk Change Default = 0x01 on VCC POR
REG OFFSET (Type) 0x18
DESCRIPTION
(R/W)
Force Disk Change Bit[0] Force Disk Change for FDC0 0=Inactive 1=Active Bit[1] Reserved Force Change 0 can be written to 1 but is not clearable by software. Force Change 0 is cleared on nSTEP and nDS0 DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND Force Change 0) OR nDSKCHG Setting the Force Disk Change bit active `1' forces the FDD nDSKCHG input active.
Floppy Data Rate Select Shadow
0x19 (R)
UART1 FIFO Control Shadow
0x1A (R)
INT_GEN1 Default = 0xFF on VCC POR and HARD RESET
0x1B (R/W)
Bit[7:2] Reserved Floppy Data Rate Select Shadow Bit[0] Data Rate Select 0 Bit[1] Data Rate Select 1 Bit[2] PRECOMP 0 Bit[3] PRECOMP 1 Bit[4] PRECOMP 2 Bit[5] Reserved Bit[6] Power Down Bit[7] Soft Reset UART FIFO Control Shadow 1 Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) Interrupt Generating Register 1 (Note 2) 0=Corresponding Interrupt frame driven low in the SER IRQ stream. This must be enabled through the INT_G Configuration Register. Bit[0] Reserved Bit[1] nINT1 Bit[2] nINT2 Bit[3] nINT3 Bit[4] nINT4 Bit[5] nINT5 Bit[6] nINT6 Bit[7] nINT7
Note:
To enable/disable this register see Logical Device A (0xF1)
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NAME
INT_GEN2 Default = 0xFF on VCC POR and HARD RESET
REG OFFSET (Type) 0x1C
DESCRIPTION
(R/W)
Interrupt Generating Register 2 (Note 2) 0=Corresponding Interrupt frame driven low in the SER IRQ stream. This must be enabled through the INT_G Configuration Register. Bit[0] nINT8 Bit[1] nINT9 Bit[2] nINT10 Bit[3] nINT11 Bit[4] nINT12 Bit[5] nINT13 Bit[6] nINT14 Bit[7] nINT15
Note:
UART2 FIFO Control Shadow
0x1D (R)
N/A
Note 1: Note 2:
0x1E-0x1F (R)
To enable/disable this register see Logical Device A (0xF1) UART FIFO Control Shadow 2 Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) Bits[7:0] Reserved - reads return 0
These bits are R/W bit, but have no effect on circuit operation. These bits when read indicate the current bit status. These bits are set to "0" by writing "0" to individual bit locations in this register. Producing an interrupt in the SER_IRQ stream by setting these bits to "0" overrides other interrupt sources for the SER_IRQ stream. No other functional logic in the LPC47M172 sets bits in the register. These bits are only cleared by writing "1" to the bit location.
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Chapter 9
GPIO Runtime Registers
Table 9.1 shows the runtime registers summary in the GPIO logical Device. Table 9.2 shows the runtime registers description in the GPIO logical device. These registers can only be accessed when LD_NUM bit in the TEST 7 configuration register is `0' (see Table 11.3). The register offsets are from the base address programmed in the GPIO logical device.
Table 9.1 - GPIO Runtime Registers Summary, LD_NUM = 0 REGISTER OFFSET (hex) 00 TYPE PCI Reset VCC POR VTR POR SOFT RESET REGISTER
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R
-
-
0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x04 0x04 0x04 0x04 0x05 0x00 0x00 -
-
GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 Reserved - reads return 0 GP1 GP2 Reserved - reads return 0
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D-14 15 16 17-1F
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Table 9.2 - GPIO Runtime Registers Description, LD_NUM = 0 NAME REG OFFSET (Type) 0x00 DESCRIPTION
GP10 Default = 0x01 on VTR POR
(R/W)
GP11 Default = 0x01 on VTR POR
0x01 (R/W)
GP12 Default = 0x01 on VTR POR
0x02 (R/W)
GP13 Default = 0x01 on VTR POR
0x03 (R/W)
GP14 Default = 0x01 on VTR POR
0x04 (R/W)
GP15 Default = 0x01 on VTR POR
0x05 (R/W)
GP16 Default = 0x01 on VTR POR
0x06 (R/W)
General Purpose I/O bit 1.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=FAN_TACH1 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
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NAME
GP17 Default = 0x01 on VTR POR
REG OFFSET (Type) 0x07
DESCRIPTION
(R/W)
GP20 Default = 0x04 on VTR POR Note 1
0x08 (R/W)
GP21 Default = 0x04 on VTR POR Note 1
0x09 (R/W)
GP22 Default = 0x04 on VTR POR Note 1
0x0A (R/W)
GP23 Default = 0x04 on VTR POR Note 1
0x0B (R/W)
General Purpose I/0 bit 1.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity :=1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=FAN_TACH2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= DDCSDA_5V 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 2.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[3:2] Alternate Function Select 11=Reserved 10=Either Edge Triggered Input 0 (Note 2) 01= DDCSCL_5V 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 2.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[3:2] Alternate Function Select 11=Reserved 10=Either Edge Triggered Input 0 (Note 2) 01= DDCSDA_3V 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 2.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=DDCSCL_3V 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
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NAME
GP24 Default = 0x05 on VTR POR
REG OFFSET (Type) 0x0C
DESCRIPTION
(R/W)
N/A GP1 Default = 0x00 on VTR POR
0x0D-0x14 (R) 0x15 (R/W)
General Purpose I/O bit 2.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nCDC_DWN_ENAB 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Bits[7:0] Reserved - reads return 0 General Purpose I/O Data Register 1 Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 General Purpose I/O Data Register 2 Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP23 Bit[4] GP24 Bits[7:5] Reserved Bits[7:0] Reserved - reads return 0
GP2 Default = 0x00 on VTR POR
0x16 (R/W)
N/A
Note 1:
0x17-0x1F (R)
The In/Out, Polarity and Output Type Select Bits do not apply when DDCSCL/DDCSDA signals are selected. If the EETI function is selected for this GPIO then both a high-to-low and low-to-high edge will set the PME and MSC status bits.
Note 2:
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Chapter 10 Runtime Register Block Runtime Registers
Table 10.1 shows the runtime register summary. See Table 10.2 - Runtime Register Block Runtime Registers Description. The Runtime Register Block runtime registers can only be accessed when LD_NUM bit in the TEST 7 configuration register is `1'. See "Power Control Runtime Registers" section and "GPIO Runtime Registers" section for description of these registers. Note these offsets replace the register offsets defined in the Power Control logical device and GPIO logical device when LD_NUM bit is `1'
Table 10.1 - Runtime Register Block Runtime Registers Summary REGISTER OFFSET (HEX) 00 01-03 04 05-07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1F 20 21 22 23 24 TYPE PCI RESET VCC POR VTR POR SOFT RESET REGISTER
R/W R R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R R R R R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R/W
0x01 0xFF 0xFF -
0x01 0xFF 0xFF -
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x80 0x00 0x01 0x01 0x01 0x01 0x01
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PME_STS Reserved - reads return 0 PME_EN Reserved - reads return 0 PME_STS3 PME_STS2 PME_STS1 Reserved - reads return 0 PME_EN3 PME_EN2 PME_EN1 Reserved - reads return 0 LED Keyboard Scan Code Tach1 LSB Tach1 MSB Tach2 LSB Tach2 MSB nIO_PME Register MSC_STS Force Disk Change Floppy Data Rate Select Shadow UART1 FIFO Control Shadow Interrupt Generating Register 1 Interrupt Generating Register 2 UART2 FIFO Control Shadow Reserved - reads return 0 GP10 GP11 GP12 GP13 GP14
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DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
REGISTER OFFSET (HEX) 25 26 27 28 29 2A 2B 2C 2D-34 35 36 37-3F
TYPE
PCI RESET
VCC POR
VTR POR
SOFT RESET
REGISTER
R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R
-
-
0x01 0x01 0x01 0x04 0x04 0x04 0x04 0x05 0x00 0x00 -
-
GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 Reserved - reads return 0 GP1 GP2 Reserved - reads return 0
Table 10.2 - Runtime Register Block Runtime Registers Description NAME REG OFFSET (Type) 0x00 DESCRIPTION
PME_STS Default = 0x00 on VTR POR
(R/W)
N/A PME_EN Default = 0x00 on VTR POR N/A
0x01 - 0x03 (R) 0x04 (R/W)
Bit[0] PME_Status = 0 (default) = 1 Set when LPC47M172 would normally assert the nIO_PME signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a "1" to PME_Status will clear it and cause the LPC47M172 to stop asserting nIO_PME, in enabled. Writing a "0" to PME_Status has no effect. Bits[7:0] Reserved - reads return 0 Bit[0] PME_En = 0 nIO_PME signal assertion is disabled (default) = 1 Enables LPC47M172 to assert nIO_PME signal Bit[7:1] Reserved PME_En is not affected by Vcc POR, SOFT RESET or HARD RESET Bits[7:0] Reserved - reads return 0
0x05 - 0x07 (R)
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NAME
PME_STS3 Default = 0x00 on VTR POR
REG OFFSET (Type) 0x08
DESCRIPTION
(R/W)
PME_STS2 Default = 0x00 on VTR POR
0x09 (R/W)
PME Wake Status Register 3 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP23 Bits[7:4] Reserved The PME Wake Status register is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. PME Wake Status Register 2 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect.
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NAME
PME_STS1 Default = 0x00 on VTR POR
REG OFFSET (Type) 0x0A
DESCRIPTION
(R/W)
N/A PME_EN3 Default = 0x00 on VTR POR
0x0B (R) 0x0C (R/W)
PME Wake Status Register 1 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] Reserved (Note 1) Bit[1] RI2 Bit[2] RI1 Bit[3] KBD Bit[4] MOUSE Bit[5] SPEKEY (Wake on specific key) Bit[6] FAN_TACH1 (note) Bit[7] FAN_TACH2 (note) The PME Wake Status register is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. Note: When the GP1x/FAN_TACHx pin is configured as a GPIO (GPIO control register bit 2 = 0), the associated PME status bit will never be set. When the pin is configured for the tachometer function (GPIO control register bit 2 = 1) and then the function is switched to the GPIO function, the associated PME status bit will be cleared. Bits[7:0] Reserved - reads return 0 PME Wake Status Register 3 This register is used to enable individual LPC47M172 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP23 Bits[7:4] Reserved The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET.
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NAME
PME_EN2 Default = 0x00 on VTR POR
REG OFFSET (Type) 0x0D
DESCRIPTION
(R/W)
PME_EN1 Default = 0x00 on VTR POR
0x0E (R/W)
N/A
0x0F (R)
PME Wake Enable Register 2 This register is used to enable individual LPC47M172 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET. PME Wake Enable Register 1 This register is used to enable individual PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] Reserved (Note 1) Bit[1] RI2 Bit[2] RI1 Bit[3] KBD Bit[4] MOUSE Bit[5] SPEKEY (Wake on specific key) Bit[6] FAN_TACH1 Bit[7] FAN_TACH2 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET. Bits[7:0] Reserved - reads return 0
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NAME
LED Default = 0x03 on VTR POR
REG OFFSET (Type) 0x10
DESCRIPTION
LED Register Bit[0] GRN_YLW 0 = Select YLW_LED if nSLP_S5 if high 1 = Select GRN_LED if nSLP_S5 is high Bit[1] SDY_BLK 0 = Blink at 0.67 Hz with 39.6% duty cycle (0.59375 sec high, 0.90625 low) if nSLP_S5 is high 1 = Steady if nSLP_S5 is high Bit[7:2] Reserved Keyboard Scan Code Bit[0] LSB of Scan Code ... ... ... Bit[7] MSB of Scan Code This register is least significant 8-bit of the 16-bit Fan Tachometer 1 reading. Bit[0] FAN_TACH1 Reading Bit 0 ... Bit[7] FAN_TACH1 Reading Bit 7 This register is most significant 8-bit of the 16-bit Fan Tachometer 1 reading. Bit[0] FAN_TACH1 Reading Bit 8 ... Bit[7] FAN_TACH1 Reading Bit 15 This register is least significant 8-bit of the 16-bit Fan Tachometer 2 reading. Bit[0] FAN_TACH2 Reading Bit 0 ... Bit[7] FAN_TACH2 Reading Bit 7 This register is most significant 8-bit of the 16-bit Fan Tachometer 2 reading. Bit[0] FAN_TACH2 Reading Bit 8 ... Bit[7] FAN_TACH2 Reading Bit 15 Bit[0] Reserved Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain (default) 0=Push Pull
(R/W)
Keyboard Scan Code Default = 0x00 on VTR POR Tach1 LSB Default = 0x00 on VTR POR Tach1 MSB Default = 0x00 on VTR POR Tach2 LSB Default = 0x00 on VTR POR Tach2 MSB Default = 0x00 on VTR POR nIO_PME Register Default = 0x80 on VTR POR
0x11 (R/W)
0x12 (R)
0x13 (R)
0x14 (R)
0x15 (R)
0x16 (R/W)
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NAME
MSC_STS Default = 0x00 on VTR POR
REG OFFSET (Type) 0x17
DESCRIPTION
(R/W)
Force Disk Change Default = 0x01 on VCC POR
0x18 (R/W)
Miscellaneous Status Register Bits[1:0] can be cleared by writing a 1 to their position (writing a 0 has no effect). Bit[0] Either Edge Triggered Interrupt Input 0 Status. This bit is set when an edge occurs on the GP21 pin. Bit[1] Either Edge Triggered Interrupt Input 1 Status. This bit is set when an edge occurs on the GP22 pin. Bit[7:2] Reserved. This bit always returns zero. Force Disk Change Bit[0] Force Disk Change for FDC0 0=Inactive 1=Active Bit[1] Reserved Force Change 0 can be written to 1 but is not clearable by software. Force Change 0 is cleared on nSTEP and nDS0 DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND Force Change 0) OR nDSKCHG Setting the Force Disk Change bit active `1' forces the FDD nDSKCHG input active. Bit[7:2] Reserved Floppy Data Rate Select Shadow Bit[0] Data Rate Select 0 Bit[1] Data Rate Select 1 Bit[2] PRECOMP 0 Bit[3] PRECOMP 1 Bit[4] PRECOMP 2 Bit[5] Reserved Bit[6] Power Down Bit[7] Soft Reset UART FIFO Control Shadow 1 Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB)
Floppy Data Rate Select Shadow
0x19 (R)
UART1 FIFO Control Shadow
0x1A (R)
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NAME
INT_GEN1 Default = 0xFF on VCC POR and HARD RESET
REG OFFSET (Type) 0x1B
DESCRIPTION
(R/W)
Interrupt Generating Register 1 (Note 2) 0=Corresponding Interrupt frame driven low in the SER IRQ stream. This must be enabled through the INT_G Configuration Register. Bit[0] Reserved Bit[1] nINT1 Bit[2] nINT2 Bit[3] nINT3 Bit[4] nINT4 Bit[5] nINT5 Bit[6] nINT6 Bit[7] nINT7
Note: To enable/disable this register see Logical Device A (0xF1) Interrupt Generating Register 2 (Note 2) 0=Corresponding Interrupt frame driven low in the SER IRQ stream. This must be enabled through the INT_G Configuration Register. Bit[0] nINT8 Bit[1] nINT9 Bit[2] nINT10 Bit[3] nINT11 Bit[4] nINT12 Bit[5] nINT13 Bit[6] nINT14 Bit[7] nINT15 Note: To enable/disable this register see Logical Device A (0xF1) Bits[7:0] Reserved - reads return 0
INT_GEN2 Default = 0xFF on VCC POR and HARD RESET
0x1C (R/W)
N/A UART2 FIFO Control Shadow
0x1D-0x1F (R) 0x1D (R)
N/A GP10 Default = 0x01 on VTR POR
0x1F (R) 0x20 (R/W)
UART FIFO Control Shadow 2 Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) Bits[7:0] Reserved - reads return 0 General Purpose I/O bit 1.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
NAME
GP11 Default = 0x01 on VTR POR
REG OFFSET (Type) 0x21
DESCRIPTION
(R/W)
GP12 Default = 0x01 on VTR POR
0x22 (R/W)
GP13 Default = 0x01 on VTR POR
0x23 (R/W)
GP14 Default = 0x01 on VTR POR
0x24 (R/W)
GP15 Default = 0x01 on VTR POR
0x25 (R/W)
GP16 Default = 0x01 on VTR POR
0x26 (R/W)
General Purpose I/O bit 1.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=FAN_TACH1 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
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NAME
GP17 Default = 0x01 on VTR POR
REG OFFSET (Type) 0x27
DESCRIPTION
(R/W)
GP20 Default = 0x04 on VTR POR Note 3
0x28 (R/W)
GP21 Default = 0x04 on VTR POR Note 3
0x29 (R/W)
GP22 Default = 0x04 on VTR POR Note 3
0x2A (R/W)
General Purpose I/0 bit 1.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity :=1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=FAN_TACH2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= DDCSDA_5V 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 2.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[3:2] Alternate Function Select 11=Reserved 10=Either Edge Triggered Input 0 (Note 4) 01= DDCSCL_5V 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 2.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[3:2] Alternate Function Select 11=Reserved 10=Either Edge Triggered Input 0 (Note 4) 01= DDCSDA_3V 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
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Advanced I/O Controller with Motherboard GLUE Logic Datasheet
NAME
GP23 Default = 0x04 on VTR POR Note 3
REG OFFSET (Type) 0x2B
DESCRIPTION
(R/W)
GP24 Default = 0x05 on VTR POR
0x2C (R/W)
N/A GP1 Default = 0x00 on VTR POR
0x2D-0x34 (R) 0x35 (R/W)
General Purpose I/O bit 2.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=DDCSCL_3V 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 2.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nCDC_DWN_ENAB 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Bits[7:0] Reserved - reads return 0 General Purpose I/O Data Register 1 Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 General Purpose I/O Data Register 2 Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP23 Bit[4] GP24 Bits[7:5] Reserved Bits[7:0] Reserved - reads return 0
GP2 Default = 0x00 on VTR POR
0x36 (R/W)
N/A
0x37-0x3F (R)
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Chapter 11 Configuration
The Configuration of the LPC47M172 is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The LPC47M172 is designed for motherboard applications in which the resources required by their components are known. With its flexible resource allocation architecture, the LPC47M172 allows the BIOS to assign resources at POST.
11.1
System Elements
11.1.1 Primary Configuration Address Decoder
After a hard reset (nPCI_RESET pin asserted) or Vcc Power On Reset the LPC47M172 is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the LPC47M172 into Configuration Mode. The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports are only valid when the LPC47M172 is in Configuration Mode. The CONFIG PORT's I/O address is set to 0x02E at power-up. Once powered up the configuration port base address can be changed through configuration registers CR26 and CR27. The INDEX and DATA ports are effective only when the chip is in the Configuration State.
PORT NAME CONFIG PORT (Note) INDEX PORT (Note) DATA PORT Note: BASE ADDRESS 0x02E 0x02E INDEX PORT + 1 TYPE Write Read/Write Read/Write
The configuration port base address can be relocated through CR26 and CR27.
11.1.2 Entering the Configuration State
The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = <0x55>
11.1.3 Exiting the Configuration State
The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = <0xAA>
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11.1.4 Configuration Sequence
To program the configuration registers, the following sequence must be followed: 1. 2. 3. Enter Configuration Mode Configure the Configuration Registers Exit Configuration Mode.
11.1.5 Enter Configuration Mode
To place the chip into the Configuration State the Config Key is sent to the chip's CONFIG PORT. The config key consists of 0x55 written to the CONFIG PORT. Once the configuration key is received correctly the chip enters into the Configuration State (The auto Config ports are enabled).
11.1.6 Configuration Mode
The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports. In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX PORT address + 1. The desired configuration registers are accessed in two steps: a) b)
Note:
Write the index of the Logical Device Number Configuration Register (i.e., 0x00 for FDC) to the INDEX PORT and then write the number of the desired logical device to the DATA PORT Write the address of the desired configuration register within the logical device to the INDEX PORT and then write or read the configuration register through the DATA PORT.
If accessing the Global Configuration Registers, step (a) is not required.
11.1.7 Exit Configuration Mode
To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State.
Note:
Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter the Configuration State.
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11.1.8 Programming Example
The following is an example of a configuration program in Intel 8086 assembly language. ;-------------------------------------------------. ; ENTER CONFIGURATION MODE | ;-------------------------------------------------` MOV DX,02EH MOV AX,055H OUT DX,AL ;-----------------------------------------------. ; CONFIGURE REGISTER CRE0, | ; LOGICAL DEVICE 8 | ;-----------------------------------------------` MOV DX,02EH MOV AL,07H OUT DX,AL ;Point to LD# Config Reg MOV DX,02FH MOV AL, 08H OUT DX,AL;Point to Logical Device 8 ; MOV DX,02EH MOV AL,E0H OUT DX,AL ; Point to CRE0 MOV DX,02fH MOV AL,02H OUT DX,AL ; Update CRE0 ;------------------------------------------------. ; EXIT CONFIGURATION MODE | ;-----------------------------------------------` MOV DX,02EH MOV AX,0AAH OUT DX,AL
Notes: HARD RESET: nPCI_RESET pin asserted SOFT RESET: Bit 0 of Configuration Control register set to one All host accesses are blocked for 500s after Vcc POR (see Power-up Timing Diagram) LD_NUM Bit
The LD_NUM bit in the TEST 7 global configuration register (0x29) is used to select between the logical device numbering in the LPC47M172. LD_NUM is determined by the state of pin 117 as described in Chapter 2. See the TEST 7 register for LD_NUM bit description. Table 11.1 and Table 11.2 summarize the logical device registers when LD_NUM bit is 0 and 1.
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Table 11.1 - LPC47M172 Configuration Registers Summary, LD_NUM bit = 0 INDEX TYPE PCI RESET SOFT CONFIGURATION REGISTER RESET GLOBAL CONFIGURATION REGISTERS 0x00 0x00 Config Control VCC POR VTR POR
0x02 0x03 0x07 0x20 0x21 0x22 0x23 0x24 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x60 0x61 0x70 0x74 0xF0 0xF1 0xF2 0xF4 0xF8 0x30 0x60 0x61 0x70 0x74 0xF0 0xF1
W R R/W R R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0x00 0x00 0x14 0x04 0x00 0x44 0x2E 0x00 0x00 -
0x00 0x14 0x04 0x00 0x44 0x2E 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x14 0x04 0x00 0x44 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x14 0x04 0x00 -
Reserved - reads return 0 Logical Device Number Device ID - hard wired Device Rev - hard wired Power Control Reserved - reads return 0 OSC Configuration Port Address Byte 0 (Low Byte) Configuration Port Address Byte 1 (High Byte) TEST 8 TEST 7 TEST 6 TEST 4 TEST 5 TEST 1 TEST 2
0x00 0x00 TEST 3 LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD) 0x00 0x00 0x00 0x00 Activate 0x03 0x03 0x03 0x03 Primary Base I/O Address High Byte 0xF0 0xF0 0xF0 0xF0 Primary Base I/O Address Low Byte 0x06 0x06 0x06 0x06 Primary Interrupt Select 0x02 0x0E 0x00 0xFF 0x00 0x02 0x0E 0x00 0xFF 0x00 0x02 0x0E 0x00 0xFF 0x00 0x02 DMA Channel Select FDD Mode Register FDD Option Register FDD Type Register FDD0
0x24 0x24 0x24 FDC Mapping Register LOGICAL DEVICE 1 CONFIGURATION REGISTERS (Parallel Port) 0x00 0x00 0x00 0x00 Activate 0x00 0x00 0x00 0x00 Primary Base I/O Address High Byte 0x00 0x00 0x00 0x00 Primary Base I/O Address Low Byte 0x00 0x00 0x00 0x00 Primary Interrupt Select 0x04 0x3C 0x00 0x04 0x3C 0x00 0x04 0x3C 0x00
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0x04 -
DMA Channel Select Parallel Port Mode Register Parallel Port Mode Register 2
SMSC LPC47M172
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
INDEX
TYPE
PCI RESET
VCC POR
VTR POR
SOFT RESET
CONFIGURATION REGISTER
0xF8 0x30 0x60 0x61 0x70 0xF0 0xF1 0xF2 0x30 0x60 0x61 0x70 0xF0 0x30 0x60 0x61 0XF0 0xF1 0x30 0x70 0x30 0x70 0xF0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0x08 0x08 0x08 PP Mapping Register LOGICAL DEVICE 2 CONFIGURATION REGISTERS (Serial Port 2) 0x00 0x00 0x00 0x00 0x00 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
-
Activate Primary Base I/O Address High Byte Primary Base I/O Address Low Byte Primary Interrupt Select Serial Port 2 Mode Register IR Options Register IR Half Duplex Timeout Activate Primary Base I/O Address High Byte Primary Base I/O Address Low Byte Primary Interrupt Select
LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Serial Port 1)
0x00 0x00 0x00 0x00
0x00 0x00 0x00 Serial Port 1 Mode Register LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Power Control) 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0X00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Activate Primary Base I/O Address High Byte Primary Base I/O Address Low Byte CLOCKI32 INT_G Register Activate Primary Interrupt Select Activate Primary Interrupt Select
LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Mouse)
LOGICAL DEVICE 6 CONFIGURATION REGISTERS (Keyboard)
0x30 0x60 0x61
Note: Note 1:
R/W R/W R/W
0x00 KRESET and GateA20 Select (Note 1) LOGICAL DEVICE 7 CONFIGURATION REGISTERS (GPIO) 0x00 0x00 0x00 0x00 Activate 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Primary Base I/O Address High Byte Primary Base I/O Address Low Byte
Reserved registers are read-only, reads return 0. Bits[7:5] of this register reset on VTR POR only.
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Table 11.2 - LPC47M172 Configuration Register Summary, LD_NUM=1 INDEX TYPE PCI RESET SOFT RESET GLOBAL CONFIGURATION REGISTERS 0x00 0x00 0x00 0x00 0x00 0x14 0x14 0x14 0x04 0x04 0x04 0x00 0x00 0x00 0x44 0x44 0x2E VCC POR VTR POR CONFIGURATION REGISTER
0x02 0x03 0x07 0x20 0x21 0x22 0x23 0x24 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x60 0x61 0x70 0x74 0xF0 0xF1 0xF2 0xF4 0xF8
W R R/W R R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0x00 0x00 0x14 0x04 0x00 0x44 0x2E
Config Control Reserved - reads return 0 Logical Device Number Device ID - hard wired Device Rev - hard wired Power Control Reserved - reads return 0 OSC Configuration Port Address Byte 0 (Low Byte) 0x00 0x00 Configuration Port Address Byte 1 (High Byte) 0x00 0x00 TEST 8 0x01 0x01 0x01 TEST 7 0x00 0x00 TEST 6 0x00 0x00 TEST 4 0x00 0x00 TEST 5 0x00 0x00 TEST 1 0x00 0x00 TEST 2 0x00 0x00 TEST 3 LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD) 0x00 0x00 0x00 0x00 Activate 0x03 0x03 0x03 0x03 Primary Base I/O Address High Byte 0xF0 0xF0 0xF0
0x30 0x60 0x61 0x70 0xF0 0xF1 0xF2
R/W R/W R/W R/W R/W R/W R/W
Primary Base I/O Address Low Byte 0x06 0x06 0x06 0x06 Primary Interrupt Select 0x02 0x02 0x02 0x02 DMA Channel Select 0x0E 0x0E 0x0E FDD Mode Register 0x00 0x00 0x00 FDD Option Register 0xFF 0xFF 0xFF FDD Type Register 0x00 0x00 0x00 FDD0 0x24 0x24 0x24 TEST9 LOGICAL DEVICE 1 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (Serial Port 2) 0x00 0x00 0x00 0x00 Activate 0x00 0x00 0x00 0x00 0x02 0x03 0x00 0x00 0x00 0x00 0x02 0x03 0x00 0x00 0x00 0x00 0x02 0x03
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0xF0
0x00 0x00 0x00
-
Primary Base I/O Address High Byte Primary Base I/O Address Low Byte Primary Interrupt Select Serial Port 2 Mode Register IR Options Register IR Half Duplex Timeout
SMSC LPC47M172
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic Datasheet
INDEX
TYPE
0x30 0x60 0x61 0x70 0x74 0xF0 0xF1 0xF8 0x30 0x60 0x61 0x70 0xF0
0x30 0x70 0x72 0xF0
0x30 0x60 0x61 0XF0 0xF1
SOFT CONFIGURATION REGISTER RESET LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) R/W 0x00 0x00 0x00 0x00 Activate R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address High Byte R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address Low Byte R/W 0x00 0x00 0x00 0x00 Primary Interrupt Select R/W 0x04 0x04 0x04 0x04 DMA Channel Select R/W 0x3C 0x3C 0x3C Parallel Port Mode Register R/W 0x00 0x00 0x00 Parallel Port Mode Register 2 R/W 0x08 0x08 0x08 TEST10 LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1) R/W 0x00 0x00 0x00 0x00 Activate R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address High Byte R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address Low Byte R/W 0x00 0x00 0x00 0x00 Primary Interrupt Select R/W 0x00 0x00 0x00 Serial Port 1 Mode Register LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 6 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 7 CONFIGURATION REGISTERS (Keyboard) R/W 0x00 0x00 0x00 0x00 Activate R/W 0x00 0x00 0x00 0x00 Primary Interrupt Select R/W 0x00 0x00 0x00 0x00 Secondary Interrupt Select R/W 0x00 0x00 0x00 KRESET and GateA20 Select (Note 1) LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 9 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE A CONFIGURATION REGISTERS (Runtime Register Block) R/W 0x00 0x00 0x00 0x00 Activate R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address High Byte R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address Low Byte R/W 0X00 CLOCKI32 R/W 0x00 0x00 0x00 0x00 INT_G Register LOGICAL DEVICE B CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE C CONFIGURATION REGISTERS (Reserved) PCI RESET VCC POR VTR POR
Note: Note 1:
Reserved registers are read-only, reads return 0. Bits[7:6, 5 and 1] of KRESET and GateA20 Select register reset on VTR POR only.
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11.2
Chip Level (Global) Control/Configuration Registers[0x00-0x2F]
The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero when read. The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the selected register. These registers are accessible only in the Configuration Mode.
Table 11.3 - Chip Level Registers REGISTER ADDRESS DESCRIPTION CHIP (GLOBAL) CONTROL REGISTERS 0x00 Reserved - Writes are ignored, reads return 0. 0x01 0x02 W The hardware automatically clears this bit after the write, there is no need for software to clear the bit. Bit 0 = 1: Soft Reset. Bits 7:1 Reserved Refer to the "Configuration Registers" table for the soft reset value for each register.
Config Control Default = 0x00 on VCC POR, VTR POR and HARD RESET
0x03 - 0x06 Reserved - Writes are ignored, reads return 0. Logical Device # Default = 0x00 on VCC POR, VTR POR, SOFT RESET and HARD RESET Card Level Reserved Device ID Hard wired = 0x14 Device Rev Hard wired = Current Revision 0x07 R/W A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. Note: The Activate command operates only on the selected logical device.
0x08 - 0x1F Reserved - Writes are ignored, reads return 0.
CHIP LEVEL, SMSC DEFINED 0x20 R A read only register which provides device identification. Bits[7:0] = 0x14 when read.
0x21 R
A read only register which provides device revision information. Bits[7:0] = current revision when read.
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REGISTER
PowerControl Default = 0x00 on VCC POR, VTR POR, SOFT RESET and HARD RESET
ADDRESS DESCRIPTION CHIP (GLOBAL) CONTROL REGISTERS 0x22 R/W Bit[0] FDC Power Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Power Bit[4] Serial Port 1 Power Bit[5] Serial Port 2 Power Bit[6] Reserved Bit[7] Reserved
OSC Default = 0x44, on VCC POR, VTR POR and HARD RESET
0x23 R 0x24 R/W
0 = Power Off or Disabled 1 = Power On or Enabled Reserved - Writes are ignored, reads return 0. Bit[0] Reserved Bit [1] PLL Control = 0 PLL is on (backward Compatible) = 1 PLL is off Bits[3:2] OSC = 01Osc is on, BRG clock is on. = 10Same as above (01) case. = 00Osc is on, BRG Clock Enabled. = 11Osc is off, BRG clock is disabled. Bit [5:4] Reserved, set to zero Bit [6] 16-Bit Address Qualification = 0 12-Bit Address Qualification = 1 16-Bit Address Qualification Note: For normal operation, bit 6 should be set. Bit[7] Reserved Reserved - Writes are ignored, reads return 0. Bit[7:1] Configuration Address Bits [7:1] Bit[0] = 0
Chip Level Vendor Defined Configuration Address Byte 0 Default =0x2E on VCC POR and HARD RESET Configuration Address Byte 1 Default = 0x00 on VCC POR and HARD RESET TEST 8 Default = 0x00 on VCC POR and VTR POR
0x25 0x26
0x27
Bit[7:0] Configuration Address Bits [15:8] See Note 1
0x28 R/W
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
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REGISTER
TEST 7 Default = 0x00 (when pin 117 is NC) 0x01(when pin 117 is connected to VTR) on VCC POR, VTR POR and HARD RESET
ADDRESS DESCRIPTION CHIP (GLOBAL) CONTROL REGISTERS 0x29 R/W Bit[0] LD_NUM = 0 New LD Numbering (selected when pin 117 is NC) = 1 SMSC LD Numbering (selected when pin 117 is connected to VTR)
Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit as follows: The pin has an internal pull-down resistor that selects the non-SMSC mode. To select this mode, the pin should be left unconnected. This configuration clears the LD_NUM bit to `0' and the associated functionality corresponds to the existing functionality in the part when the LD_NUM bit=0. Connecting this pin to VTR will select the SMSC mode of the logical device numbering. This configuration sets the LD_NUM bit to `1' and the associated functionality corresponds to the existing functionality in the part when the LD_NUM bit=1. Bits[7:1] Reserved Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
TEST 6 Default = 0x00, on VCC POR and VTR POR TEST 4 Default = 0x00, on VCC POR and VTR POR TEST 5 Default = 0x00, on VCC POR and VTR POR
0x2A R/W
0x2B R/W
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
0x2C R/W
TEST 1 Default = 0x00, on VCC POR and VTR POR TEST 2 Default = 0x00, on VCC POR and VTR POR
0x2D R/W
Bit[7] Test Mode: Reserved for SMSC. Users should not write to this bit, may produce undesired results. Bit[6] 8042 Reset: 1 = put the 8042 into reset 0 = take the 8042 out of reset Bits[5:0] Test Mode: Reserved for SMSC. Users should not write to this bit, may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
0x2E R/W
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
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REGISTER
TEST 3 Default = 0x00, on VCC POR and VTR POR
Note 1:
ADDRESS DESCRIPTION CHIP (GLOBAL) CONTROL REGISTERS 0x2F R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
To allow the selection of the configuration address to a user defined location, these Configuration Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is, the address must be on an even byte boundary. As soon as both bytes are changed, the configuration space is moved to the specified location with no delay (Note: Write byte 0, then byte 1; writing CR27 changes the base address).
11.3
Logical Device Configuration/Control Registers [0x30-0xFF]
These registers are used to access the registers that are assigned to each logical device. The logical devices are Floppy, Parallel, Serial Port, Keyboard Controller, Power Control and GPIO. A separate set (bank) of control and configuration registers exists for each logical device and is selected with the Logical Device # Register (0x07). The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the DATA PORT. The Logical Device registers are accessible only when the device is in the Configuration State. The logical register addresses are shown in the table below.
Table 11.4 - Logical Device Registers LOGICAL DEVICE REGISTER Activate ADDRESS DESCRIPTION
(0x30)
Default = 0x00 on VCC POR, VTR POR, HARD RESET and SOFT RESET
Bits[7:1] Reserved, set to zero. Bit[0] =1 Activates the logical device currently selected through the Logical Device # register. =0 Logical device currently selected is inactive
Note: A logical device will be active and powered up according to the following equation unless otherwise specified:
Logical Device Control Logical Device Control Memory Base Address
(0x31-0x37) (0x38-0x3F) (0x40-0x5F)
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET). The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the other. Reserved - Writes are ignored, reads return 0. Vendor Defined - Reserved - Writes are ignored, reads return 0. Reserved - Writes are ignored, reads return 0.
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LOGICAL DEVICE REGISTER I/O Base Address
ADDRESS
DESCRIPTION
(0x60-0x6F) 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0]
(see Device Base I/O Address Table) Default = 0x00 on VCC POR, VTR POR, HARD RESET and SOFT RESET
Registers 0x60 and 0x61 set the base address for the device. If more than one base address is required, the second base address is set by registers 0x62 and 0x63. Refer to Table 11.7 and Table 11.8 for the number of base address registers used by each device. Unused registers will ignore writes and return zero when read.
Note: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored. 0x70 is implemented for each logical device. Refer to Interrupt Configuration Register description. Only the keyboard controller uses Interrupt Select register 0x72. Unused register (0x72) will ignore writes and return zero when read. Interrupts default to edge high (ISA compatible).
Interrupt Select Defaults : 0x70 = 0x00 or 0x06 (Note) on VCC POR, VTR POR, HARD RESET and SOFT RESET 0x72 = 0x00, on VCC POR, VTR POR, HARD RESET and SOFT RESET
(0x70,0x72)
Refer to Table 11.5
Note: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
(0x71,0x73)
DMA Channel Select Default = 0x02 or 0x04 (Note) on VCC POR, VTR POR, HARD RESET and SOFT RESET 32-Bit Memory Space Configuration Logical Device
(0x74,0x75)
Reserved - not implemented. These register locations ignore writes and return zero when read. Only 0x74 is implemented for FDC and Parallel port. 0x75 is not implemented and ignores writes and returns zero when read. Refer to Table 11.6.
Note: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical device 4 (UART) is 0x04. Reserved - not implemented. These register locations ignore writes and return zero when read. Reserved - not implemented. These register locations ignore writes and return zero when read. Reserved - Vendor Defined (see SMSC defined Logical Device Configuration Registers). Reserved
(0x76-0xA8)
(0xA9-0xDF)
Logical Device Configuration Reserved
(0xE0-0xFE)
0xFF
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Table 11.5 - Primary Interrupt Select Configuration Register Description NAME Primary Interrupt Select REG INDEX 0x70 (R/W) DEFINITION Bits[3:0] selects which interrupt is used for the primary Interrupt. 0x00= no interrupt selected 0x01= IRQ1 0x02= IRQ2 0x03= IRQ3 0x04= IRQ4 0x05= IRQ5 0x06= IRQ6 0x07= IRQ7 0x08= IRQ8 0x09= IRQ9 0x0A= IRQ10 0x0B= IRQ11 0x0C= IRQ12 0x0D= IRQ13 0x0E= IRQ14 0x0F= IRQ15 Note: All interrupts are edge high (except ECP/EPP)
Default=0x00 or 0x06 (Note 1) on VCC POR, VTR POR, HARD RESET and SOFT RESET
Notes:
An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND : For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr. For the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by setting the OUT2 bit in the UART's Modem Control (MCR) Register. For the KYBD logical device (refer to the KYBD controller section of this spec). IRQs are disabled if not used/selected by any Logical Device. Refer to Note A. All IRQ's are available in Serial IRQ mode.
Note 1:
The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Table 11.6 - DMA Channel Select Configuration Register Description NAME DMA Channel Select REG INDEX 0x74 (R/W) DEFINITION Bits[2:0] select the DMA Channel. 0x00= Reserved 0x01= DMA1 0x02= DMA2 0x03= DMA3 0x04-0x07= No DMA active
Default=0x02 or 0x04 (Note 1) on VCC POR, VTR POR, HARD RESET and SOFT RESET
Notes:
A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND : - For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
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- For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr. The DMA channel must be disabled if not used/selected by any Logical Device. Refer to Note A.
Note 1:
The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical device 3 is 0x04.
Logical Device IRQ and DMA Operation
Note A.
1.
IRQ and DMA Enable and Disable: Any time the IRQ or DMA channel for a logical block is disabled by a register bit in that logical block, the IRQ and/or DMA channel must be disabled. This is in addition to the IRQ and DMA channel disabled by the Configuration Registers (active bit or address not valid). A. FDC: For the following cases, the IRQ and DMA channel used by the FDC are disabled. Digital Output Register (Base+2) bit D3 (DMAEN) set to "0". The FDC is in power down (disabled). B. Serial Port: Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port interrupt is disabled. C. Parallel Port: I. SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is disabled. ii. ECP Mode: (1) (DMA) dmaEn from ecr register. See table. (2) IRQ - See table.
MODE IRQ (FROM ECR REGISTER) CONTROLLED BY 000 PRINTER IRQE 001 SPP IRQE 010 FIFO (on) 011 ECP (on) 100 EPP IRQE 101 RES IRQE 110 TEST (on) 111 CONFIG IRQE Keyboard Controller: Refer to the KBD section of this spec. DMA CONTROLLED BY
dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn
D.
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11.4
Logical Device I/O Address
Table 11.7 and Table 11.8 summarize the logical device I/O addresses when LD_NUM bit is 0 and 1.
Table 11.7 - Logical Device I/O Address, LD_NUM Bit = 0
LOGICAL DEVICE NUMBER 0x00
LOGICAL DEVICE FDC
REGISTER INDEX 0x60,0x61
BASE I/O RANGE (NOTE 1) [0x0100:0x0FF8]
FIXED BASE OFFSETS
ON 8 BYTE BOUNDARIES
0x01
Parallel Port
0x60,0x61
[0x0100:0x0FFC] ON 4 BYTE BOUNDARIES (EPP Not supported) or [0x0100:0x0FF8] ON 8 BYTE BOUNDARIES (all modes supported, EPP is only available when the base address is on an 8byte boundary) [0x0100:0x0FF8] ON 8 BYTE BOUNDARIES
0x02
Serial Port 2
0x60,0x61
0x03
Serial Port
0x60,0x61
[0x0100:0x0FF8] ON 8 BYTE BOUNDARIES
0x04
Power Control
0x60,0x61
[0x0000:0x0FE0] on 32-byte boundaries
0x05 0x06 0x07
Mouse KYBD GPIO
n/a n/a 0x60,0x61
Not Relocatable Not Relocatable Fixed Base Address: 60,64 [0x0000:0x0FE0] on 32-byte boundaries
+0 : SRA +1 : SRB +2 : DOR +3 : TSR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR +0 : Data/ecpAfifo +1 : Status +2 : Control +400h : cfifo/ecpDfifo/tfifo/cnfgA +401h : cnfgB +402h : ecr +3 : EPP Address +4 : EPP Data 0 +5 : EPP Data 1 +6 : EPP Data 2 +7 : EPP Data 3 +0 : RB/TB/LSB div +1 : IER/MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR +0 : RB/TB/LSB div +1 : IER/MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR +00 : PME Status . . . +1F : Reserved (See Table 8.1 for Full List) +0 : Data Register +4 : Command/Status Reg. +0 : Data Register +4 : Command/Status Reg. +00 : GP10 . . +1F : Reserved (See Table 9.1 for Full List)
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LOGICAL DEVICE NUMBER Config. Port
LOGICAL DEVICE Config. Port
REGISTER INDEX 0x26, 0x27
BASE I/O RANGE (NOTE 1) 0x0100:0x0FFE On 2 byte boundaries
FIXED BASE OFFSETS See Configuration Register Summary table. Accessed through the index and DATA ports located at the Configuration Port address and the Configuration Port address +1 respectively.
Note 1:
This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the OSC Global Configuration Register (CR24) must be set to `1' and Address Bits [A15:A12] must be `0' for 16 bit address qualification.
Table 11.8 - Logical Device I/O Address, LD_NUM Bit = 1 LOGICAL DEVICE NUMBER 0x00 LOGICAL DEVICE FDC REGISTER INDEX BASE I/O RANGE (NOTE 1) [0x0100:0x0FF8] FIXED BASE OFFSETS
0x60,0x61
ON 8 BYTE BOUNDARIES
0x01 0x02
Reserved Serial Port 2
n/a 0x60,0x61
n/a [0x0100:0x0FF8] ON 8 BYTE BOUNDARIES
0x03
Parallel Port
0x60,0x61
[0x0100:0x0FFC] ON 4 BYTE BOUNDARIES (EPP Not supported) or [0x0100:0x0FF8] ON 8 BYTE BOUNDARIES (all modes supported, EPP is only available when the base address is on an 8byte boundary)
+0 : SRA +1 : SRB +2 : DOR +3 : TSR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR n/a +0 : RB/TB/LSB div +1 : IER/MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR +0 : Data/ecpAfifo +1 : Status +2 : Control +400h : cfifo/ecpDfifo/tfifo/cnfgA +401h : cnfgB +402h : ecr +3 : EPP Address +4 : EPP Data 0 +5 : EPP Data 1 +6 : EPP Data 2 +7 : EPP Data 3
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LOGICAL DEVICE NUMBER 0x04
LOGICAL DEVICE Serial Port 1
REGISTER INDEX
0x60,0x61
BASE I/O RANGE (NOTE 1) [0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
0x05 0x06 0x07 0x08 0x09 0x0A
Reserved Reserved KYBD Reserved Reserved Runtime Register Block
n/a n/a n/a n/a n/a 0x60,0x61
n/a n/a Not Relocatable Fixed Base Address: 60,64 n/a n/a [0x0000:0x0FC0] on 64-byte boundaries
0x0B Config. Port
Reserved Config. Port
n/a 0x26, 0x27
n/a 0x0100:0x0FFE On 2 byte boundaries
FIXED BASE OFFSETS +0 : RB/TB/LSB div +1 : IER/MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR n/a n/a +0 : Data Register +4 : Command/Status Reg. n/a n/a +00 : PME Status . . . +3F : Reserved (See Table 10.1 for Full List) n/a See Configuration Register Summary table. Accessed through the index and DATA ports located at the Configuration Port address and the Configuration Port address +1 respectively.
Note 1:
This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the OSC Global Configuration Register (CR24) must be set to `1' and Address Bits [A15:A12] must be `0' for 16 bit address qualification.
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11.5
Logical Device Configuration Registers
The Logical Device Configuration Registers reset to their default values only on hard resets generated by VCC or VTR POR (as shown) or the nPCI_RESET signal. These registers are not affected by soft resets.
Table 11.9 - Floppy Disk Controller Logical Device Configuration Registers NAME FDD Mode Register REG INDEX 0xF0 R/W DEFINITION Bit[0] Floppy Mode =0 Normal Floppy Mode (default) =1 Enhanced Floppy Mode 2 (OS2) Bit[1] FDC DMA Mode =0 Burst Mode is enabled =1 Non-Burst Mode (default) Bit[3:2] Interface Mode = 11 AT Mode (default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit[4] FDC_SWAP 0 = Do Not Swap (default) 1 = Swap Drive 0 (nDS, nMTR pins) with Drive 1 (nDS, nMTR pins) Bit[5] Reserved, set to zero Bit[6] FDC Output Type Control =0 FDC outputs are OD12 open drain (default) =1 FDC outputs are O12 push-pull Bit[7] FDC Output Control =0 FDC outputs active (default) =1 FDC outputs tri-stated Bit[0] Forced Write Protect =0 Inactive (default) =1 FDD nWRTPRT input is forced active when either of the drives has been selected. nWRTPRT (to the FDC Core) = WP (FDC SRA register, bit 1) = (nDS0 AND Forced Write Protect) OR (nDS1 AND Forced Write Protect) OR nWRTPRT (from the FDD Interface) Bit[1] Reserved Bits[3:2] Density Select = 00 Normal (default) = 01 Normal (reserved for users) = 10 1 (forced to logic "1") = 11 0 (forced to logic "0") Bit[7:4] Reserved.
Default = 0x0E on VCC POR, VTR POR and HARD RESET
FDD Option Register Default = 0x00 on VCC POR, VTR POR and HARD RESET
0xF1 R/W
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NAME FDD Type Register
REG INDEX 0xF2 R/W
Default = 0xFF on VCC POR, VTR POR and HARD RESET 0xF3 R 0xF4 R/W
FDD0 Default = 0x00 on VCC POR, VTR POR and HARD RESET
TEST9 Default = 0x24 on VCC POR, VTR POR and HARD RESET
0xF5 R 0xF8 R/W
DEFINITION Bits[1:0] Floppy Drive A Type Bits[3:2] Reserved (could be used to store Floppy Drive B type) Bits[5:4] Reserved (could be used to store Floppy Drive C type) Bits[7:6] Reserved (could be used to store Floppy Drive D type) Reserved, Read as 0 (read only) Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] Read as 0 (read only) Bits[4:3] Data Rate Table Select: DRT1, DRT0 Bits[5] Read as 0 (read only) Bits[6] Precompensation Disable PTS =0 Use Precompensation =1 No Precompensation Bits[7] Read as 0 (read only) Reserved, Read as 0 (read only) Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
Table 11.10 - Serial Port 2 Logical Device Configuration Registers
NAME
Serial Port 2 Mode Register Default = 0x00 on VCC POR, VTR POR and HARD RESET
REG INDEX
0xF0 R/W
DEFINITION
Bit[0] MIDI Mode =0 MIDI support disabled (default) =1 MIDI support enabled Bit[1] High Speed =0 High Speed Disabled(default) =1 High Speed Enabled Bit[7:2] Reserved, set to zero
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NAME
IR Option Register Default = 0x02 on VCC POR, VTR POR and HARD RESET
REG INDEX
0xF1 R/W
DEFINITION
Bit[0] Receive Polarity =0 Active High (Default) =1 Active Low Bit[1] Transmit Polarity =0 Active High =1 Active Low (Default) Bit[2] Duplex Select =0 Full Duplex (Default) =1 Half Duplex Bits[5:3] IR Mode = 000 Standard COM Functionality (Default) = 001 IrDA = 010 ASK-IR = 011 Reserved = 1xx Reserved Bit[6] IR Location Mux =0 Use Serial port TXD2 and RXD2 (Default). The IRTX2 pin is low. =1 Use alternate IRRX2 and IRTX2 pins. The TXD2 pin is tri-state. Bit[7] Reserved, write 0. Bits [7:0] These bits set the half duplex time-out for the IR port. This value is 0 to 10msec in 100usec increments. 0= blank during transmit/receive 1= blank during transmit/receive + 100usec ...
IR Half Duplex Timeout Default = 0x03 on VCC POR, VTR POR and HARD RESET
0xF2
Table 11.11 - Parallel Port Logical Device Configuration Registers NAME PP Mode Register REG INDEX 0xF0 R/W DEFINITION Bits[2:0] Parallel Port Mode = 100 Printer Mode (default) = 000 Standard and Bi-directional (SPP) Mode = 001 EPP-1.9 and SPP Mode = 101 EPP-1.7 and SPP Mode = 010 ECP Mode = 011 ECP and EPP-1.9 Mode = 111 ECP and EPP-1.7 Mode
Default = 0x3C on VCC POR, VTR POR and HARD RESET
Bit[6:3] ECP FIFO Threshold 0111b (default) Bit[7] PP Interrupt Type Not valid when the parallel port is in the Printer Mode (100) or the Standard & Bi-directional Mode (000). = 1 Pulsed Low, released to high-Z. = 0 IRQ follows nACK when parallel port in EPP Mode or [Printer,SPP, EPP] under ECP. IRQ level type when the parallel port is in ECP, TEST, or Centronics FIFO Mode.
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NAME PP Mode Register 2
REG INDEX 0xF1 R/W
Default = 0x00 on VCC POR, VTR POR and HARD RESET TEST10 Default = 0x08 on VCC POR, VTR POR and HARD RESET 0xF8 R/W
DEFINITION Bits[3:0] Reserved. Set to zero Bit [4] TIMEOUT_SELECT = 0 TMOUT (EPP Status Reg.) cleared on write of `1' to TMOUT. = 1 TMOUT cleared on trailing edge of read of EPP Status Reg. Bits[7:5] Reserved. Set to zero. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
Table 11.12 - Serial Port 1 Logical Device Configuration Registers NAME Serial Port 1 Mode Register REG INDEX 0xF0 R/W DEFINITION
Default = 0x00 on VCC POR, VTR POR and HARD RESET
Bit[0] MIDI Mode =0 MIDI support disabled (default) =1 MIDI support enabled Bit[1] High Speed =0 High Speed Disabled(default) =1 High Speed Enabled Bit[6:2] Reserved, set to zero Bit[7] Share IRQ =0 UARTS use different IRQs =1 UARTS share a common IRQ See Note 1 below.
Note 1:
To properly share and IRQ, 1. Configure UART1 (or UART2) to use the desired IRQ. 2. Configure UART2 (or UART1) to use No IRQ selected. 3. Set the share IRQ bit.
Note:
If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs will assert when either UART generates an interrupt.
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Table 11.13 - Keyboard Logical Device Configuration Registers NAME KRST_GA20 REG INDEX DEFINITION 0xF0 KRESET and GateA20 Select R/W Bit[7] ISO_MODE = 0 Mode 1 (default) - Isolate the 8042 in hardware while the nLPCPD signal is active OR when the Keyboard and Mouse isolation bits are set by software. = 1 Mode 2 - Keyboard and mouse isolation bits set by software only. Note: the input path to the 8042 is also isolated while the nLPCPD signal is active. Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect MDAT signal to mouse wakeup (PME) logic. 1=block mouse clock and data signals into 8042 0= do not block mouse clock and data signals into 8042 Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect KDAT signal to keyboard wakeup (PME) logic. 1=block keyboard clock and data signals into 8042 0= do not block keyboard clock and data signals into 8042 Bit[4] MLATCH = 0 MINT is the 8042 MINT ANDed with Latched MINT (default) = 1 MINT is the latched 8042 MINT Bit[3] KLATCH = 0 KINT is the 8042 KINT ANDed with Latched KINT (default) = 1 KINT is the latched 8042 KINT Bit[2] Port 92 Select = 0 Port 92 Disabled = 1 Port 92 Enabled Bit[1] Reserved Bit[0] Reserved
Default = 0x00 on VCC POR, VTR POR and HARD RESET Bits[7:5] reset on VTR POR only
Table 11.14 - Power Control/Runtime Register Block Logical Device Configuration Registers NAME CLOCKI32 REG INDEX DEFINITION 0xF0 Bit[0] (CLK32_PRSN) (R/W) 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded) Bit[1] SPEKEY_EN. This bit is used to turn the logic for the "wake on specific key" feature on and off. It will disable the 32kHz clock input to the logic when turned off. The logic will draw no power when disabled. 0= "Wake on specific key" logic is on (default) 1= "Wake on specific key" logic is off Bits[7:2] are reserved
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NAME INT_G
Default = 0x00 on VCC POR, VTR POR, HARD RESET and SOFT RESET
REG INDEX DEFINITION 0xF1 Bit[7:1] Reserved R/W Bit[0] INT_G Enable 0 = Disable Interrupt Generating Registers (INT_GENx) from affecting the serial IRQ stream 1 = Enable Interrupt Generating Registers to drive one or more frames low in the SER IRQ stream Note: See Runtime Registers at offset 0x1B and 0x1C for configuring Interrupt Generating Registers.
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Chapter 12 Electrical Characteristics
12.1 Maximum Guaranteed Ratings
Maximum 3.3 Supply ............................................................................................................................ +4.1V Maximum 5V Supply ............................................................................................................................. +6.0V Voltage on any 3.3V pin, with respect to Ground ......................................................................... -0.5 to 5.5V Voltage on any 5V pin, with respect to Ground ............................................................................ -0.5 to 5.5V Operating Temperature Range .................................................................................................. 0oC to +70oC Storage Temperature Range .................................................................................................. -55o to +150oC Lead Temperature Range (lead-free, P/N LPC47N172-NW) ..................Refer to JEDEC Spec. J-STD-020B Lead Temperature Range (leaded, P/N LPC47N172-NR) ......................Refer to JEDEC Spec. J-STD-020B
Note:
Stresses above those listed above and below could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
12.2
o
Operational DC Characteristics
Table 12.1 - Operational DC Characteristics
o
(TA = 0 C to 70 C) PARAMETER I Input Buffer Low Input Level High Input Level IPU Input Buffer Low Input Level High Input Level Pull-Up IS Input Buffer Low Input Level High Input Level Schmitt Trigger Hystersis
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VIL VIH 2.0
0.8 5.5
V V
TTL Levels TTL Levels
VIL VIH PU 2.0 30
0.8 5.5
V V uA
TTL Levels TTL Levels
VIL VIH VHYS 2.2 250
0.8 5.5
V V mV
Schmitt Trigger Schmitt Trigger
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PARAMETER IS_400 Input Buffer
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
Low Input Level High Input Level Schmitt Trigger Hystersis ISPU_400 Input Buffer Low Input Level High Input Level Schmitt Trigger Hystersis Pull-Up Input Low Current Input High Current AO Analog Output Buffer
For REF5V_OUT
VIL VIH VHYS 2.2 400
0.8 5.5
V V mV
Schmitt Trigger Schmitt Trigger
VIL VIH VHYS PU ILEAKIL ILEAKIH -26 2.2 400 30
0.8 5.5
V V mV uA
Schmitt Trigger Schmitt Trigger
1 -88
uA uA
VIN = VTR VIN = 0V
Low Output Level
VOL
0.4
V
VCC5V>1.5V, VCC5V>VCC + 0.15;
High Output Level
VOH
VREF3IN -0.15
VREF3IN +0.15
V
VCC>1.5V, VCC>VCC5V + 0.15; IOH = -3.3mA
For REF5V_STBY
Low Output Level
VOL
0.4
V
V_5P0_STBY>1.5V, V_5P0_STBY>VTR + 0.15; VTR>1.5V, VTR>V_5P0_STBY + 0.15; IOH = -3.3mA
High Output Level
O8 Output Buffer
VOH
VTR-0.15
VTR+ 0.15
V
Low Output Level High Output Level OD8 Output Buffer Low Output Level High Output Level
VOL VOH 2.4
0.4
V V
IOL = 8mA IOH = -4mA
VOL VOH
0.4 Vcc+10%
V V
IOL = 8mA Open-Drain
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PARAMETER O12 Output Buffer
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
Low Output Level High Output Level OD12 Output Buffer Low Output Level High Output Level OP14 Output Buffer Low Output Level High Output Level OD24 Output Buffer Low Output Level High Output Level IO8 Input/Output Buffer Low Input Level High Input Level Low Output Level High Output Level ISO8 Input/Output Buffer Low Input Level High Input Level Schmitt Trigger Hystersis Low Output Level High Output Level
VOL VOH 2.4
0.4
V V
IOL = 12mA IOH = -6mA
VOL VOH
0.4 Vcc+10%
V V
IOL = 12mA Open-Drain
VOL VOH 2.4
0.4
V V
IOL = 14mA IOH = -14mA
VOL VOH
0.4 Vcc+10%
V V
IOL = 24mA Open-Drain
VIL VIH VOL VOH 2.4 2.0
0.8 5.5 0.4
V V V V
TTL Levels TTL Levels IOL = 8mA IOH = -4mA
VIL VIH VHYS VOL VOH 2.4 2.2 250
0.8 5.5
V V mV
Schmitt Trigger Schmitt Trigger
0.4
V
IOL = 8mA IOH = -4mA
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PARAMETER ISOD8 Input/Output Buffer
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
Low Input Level High Input Level Schmitt Trigger Hystersis Low Output Level High Output Level
IPDO8 Input Buffer
VIL VIH VHYS VOL VOH 2.2 250
0.8 5.5
V V mV
Schmitt Trigger Schmitt Trigger
0.4 Vcc+10%
V V
IOL = 8mA Open-Drain, Vcc = 5V Max
Low Input Level High Input Level Pull-Down Low Output Level High Output Level IO12 Input/Output Buffer Low Input Level High Input Level Low Output Level High Output Level IOP14 Input/Output Buffer Low Input Level High Input Level Low Output Level High Output Level IO_SW Input/Output Special Type
VIL VIH PD VOL VOH 2.0 30
0.8 5.5
V V uA
TTL Levels TTL Levels
0.4 Vcc+10%
V V
IOL = 8mA IOH = -4mA
VIL VIH VOL VOH 2.4 2.0
0.8 5.5 0.4
V V V V
TTL Levels TTL Levels IOL = 12mA IOH = -6mA
VIL VIH VOL 2.0
0.8 5.5 0.4
V V V
TTL Levels TTL Levels IOL = 14mA
VOH IOH = -14mA 2.4 V Pins of this type are connected in pairs through a switch. The switch provides a 25 ohm (max) resistance to ground when closed. See SMBus Isolation Circuitry and Voltage Translation Circuit sections for a description. Note: Vcc=5V max.
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PARAMETER IOD24 Input/Output Buffer
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
Low Input Level High Input Level Low Output Level High Output Level PCI Type Buffers (PCI_ICLK, PCI_I, PCI_O, PCI_IO) Leakage Current (ALL except IS, IS_400, ISPU_400, ISOD8, AO, O8_3V and PCI Buffers) Input High Current Input Low Current
Leakage Current (IS, IS_400, ISPU_400 and ISOD8 Buffers)
VIL VIH VOL VOH 3.3V PCI 2.1 Compatible. 2.0
0.8 5.5 0.4 Vcc+10%
V V V V
TTL Levels TTL Levels IOL = 24mA Open-Drain
ILEAKIH ILEAKIL
10 -10
uA uA
VIN = Vcc VIN = 0V
Input High Leakage Current Input Low Leakage Current
Leakage Current (AO Buffer)
ILEAKIH ILEAKIL
1 -1
uA uA
VIN = Vcc VIN = 0V
Input High Leakage Current Input Low Leakage Current Leakage Current (PCI Buffers and nRSMRST) Input High Leakage Current Input Low Leakage Current Backdrive Protect/ChiProtect (All except PCI Buffers and nRSMRST) Input High Leakage Current Input Low Leakage Current
ILEAKIH ILEAKIL
20 -20
uA uA
VIN = Vcc VIN = 0V VCC = 0V and VCC = 3.3V VIN = 3.6V Max VIN = 0V
ILEAKIH ILEAKIL
10 -10
A A
ILEAKIH ILEAKIL
10 -10
A A
VCC = 0V VIN = 5.5V Max VIN = 0V
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PARAMETER 5V Tolerant Pins (All except PCI Buffers and nRSMRST)
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
Input High Leakage Current Input Low Leakage Current
3.3V Main Supply Voltage 3.3V Main Supply Current
ILEAKIH ILEAKIL VCC ICC3
10 -10 3.6 15
A A V mA
VCC = 0V VIN = 5.5V Max VIN = 0V VCC must not be greater than 0.5V above VTR All outputs open, all inputs transitioning to/from 0V from/to 3.3V All outputs open, all inputs transitioning to/from 0V from/to 3.3V
3.0
3.3 10
3.3V Standby Supply Current 5V Standby Supply Voltage 5V Standby Supply Current Note:
ITR3
0.2
2
mA
V_5P0_S TBY ITR5
4.75 1
5.25 3
V mA
All leakage currents are measured with pins in high impedance.
12.3
Standby Power Requirements
This includes only signals that are outputs and source standby current (no OD outputs). Internal pull-ups are ignored due to their small contribution. External pull-ups are not in this analysis because they do not cause LPC47M172 to draw a discernable amount of additional power.
Application Note: The following pins are powered by VTR. If configured as output pins, the VTR current will increase if these pins are sourcing current into a load. The board designer must make allowances for this additional current based upon this board design and the loads these pins are driving. Table 12.2 - S3-S5 Standby Current
SYMBOL
REF5V_STBY nCDC_DWN_ENAB/GP24 nCDC_DWN_RST nPCIRST_OUT nPCIRST_OUT2 nIO_PME LATCHED_BF_CUT PWRGD_3V nRSMRST GP10-GP17, GP20-GP23 Total
TYPE
AO IO12 O12 OP14 OP14 O8/OD8 OP14 O8 O8 IO8
STBY MAX. CURRENT (MA) 3.3 6 6 14 14 4 0 4 4 48 103.3
NAME AND FUNCTION
Standby Reference Output CODEC Down Enable/GPIO CODEC Down Reset 3.3V Buffered copy of nPCI_RESET Second 3.3V Buffered copy of nPCI_RESET Power Management Events Signal only on for a short period of time Power Good Signal Reset for the ICH Resume Well 12 GPIOs
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12.4
Capacitance Values for Pins
MAX 20 10 20 UNIT pF pF pF TEST CONDITION All pins except pin under test tied to AC ground
CAPACITANCE TA = 25oC; fc = 1MHz; VCC = 3.3V 10% LIMITS PARAMETER SYMBOL MIN TYP Clock Input Capacitance CIN Input Capacitance CIN Output Capacitance COUT
Note:
The input capacitance of a port is measured at the connector pins.
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Chapter 13 Timing Diagrams
For the Timing Diagrams shown, the following capacitive loads are used on outputs.
NAME SER_IRQ LAD [3:0] nLDRQ nDIR nSTEP nDS0 PD[0:7] nSTROBE nALF KDAT KCLK MDAT MCLK TXD YLW_LED GRN_LED nIDE_RSTDRV nPCIRST_OUT nPCIRST_OUT2 PS_ON SCK_BJT_GATE PWRGD_3V nCDC_DWN_ENAB/ GP24 nCDC_DWN_RST CAPACITANCE TOTAL (pF)
50 50 50 240 240 240 240 240 240 240 240 240 240 50 50 50 40 40 40 50 50 50 50 50
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t1 V cc
t2 t3
A ll H o s t A ccesses
Figure 13.1 - Power-Up Timing NAME DESCRIPTION MIN TYP MAX UNITS
t1 t2 t3
Note 1:
Vcc Slew from 2.7V to 0V Vcc Slew from 0V to 2.7V All Host Accesses After Powerup (Note 1)
300 100 125 500
us us us
Internal write-protection period after Vcc passes 2.7 volts on power-up
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t1
CLOCKI
t2
t2
Figure 13.2 - Input Clock Timing NAME t1 t2 t1 DESCRIPTION Clock Cycle Time for 14.318MHZ Clock High Time/Low Time for 14.318MHz Clock Cycle Time for 32KHZ MIN TYP 69.84 35 31.25 MAX UNITS ns ns s s ns
20
t2
Clock High Time/Low Time for 32KHz Clock Rise Time/Fall Time (not shown)
15.63 5
t1
t4 t3 t2
P C I_ C L K
t5
Figure 13.3 - PCI Clock Timing NAME t1 t2 t3 t4 t5 DESCRIPTION
Period High Time Low Time Rise Time Fall Time
MIN 30 12 12
TYP
MAX 33.3
3 3
UNITS nsec nsec nsec nsec nsec
nPCI_RESET
t1
Figure 13.4 - Reset Timing NAME t1 DESCRIPTION
nPCI_RESET width
MIN 1
TYP
MAX
UNITS ms
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CLK t1 Output Delay t2 t3 Tri-State Output
Figure 13.5 - Output Timing Measurement Conditions, LPC Signals NAME DESCRIPTION t1 CLK to Signal Valid Delay - Bused Signals t2 Float to Active Delay t3 Active to Float Delay MIN 2 2 TYP MAX 11 11 28 UNITS ns ns ns
t1 CLK Input
Inputs Valid
t2
Figure 13.6 - Input Timing Measurement Conditions, LPC Signals NAME DESCRIPTION t1 Input Set Up Time to CLK - Bused Signals t2 Input Hold Time from CLK MIN 7 0 TYP MAX UNITS ns ns
PCI_CLK nLFRAME LAD[3:0]
L1 L2 Address Data TAR Sync=0110 L3 TAR
Note:
L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000
Figure 13.7 - I/O Write
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PCI_CLK nLFRAME LAD[3:0]
L1 L2 Address TAR Sync=0110 L3 Data TAR
Note:
L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000
Figure 13.8 - I/O Read
PCI_CLK nLDRQ
Start MSB LSB ACT
Figure 13.9 - DMA Request Assertion through NLDRQ
PCI_CLK LFRAME# LAD[3:0]
Start C+D CHL Size TAR Sync=0101 L1 Data TAR
Note:
L1=Sync of 0000
Figure 13.10 - DMA Write (First Byte)
PCI_CLK nLFRAME LAD[3:0]
Note:
Start C+D CHL Size Data TAR Sync=0101 L1 TAR
L1=Sync of 0000
Figure 13.11 - DMA Read (First Byte)
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nDIR
t3
nSTEP t9 nDS0
t4 t1 t2
t5
nINDEX
t6
nRDATA
t7
nWDATA
t8
Figure 13.12 - Floppy Disk Drive Timing (At Mode Only) NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 Notes: DESCRIPTION nDIR Set Up to STEP Low nSTEP Active Time Low nDIR Hold Time after nSTEP nSTEP Cycle Time nDS0 Hold Time from nSTEP Low (Note) nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low nDS0 Setup Time nDIR Low (Note) MIN TYP 4 24 96 132 20 2 40 .5 MAX UNITS X* X* X* X* X* X* ns Y* ns
0
*X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz) WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz) The DS0 setup and hold time must be met by software.
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t1 nWRITE
t2
t3 PD<7:0> t4 t5 t6 nDATASTB nADDRSTB t8 nWAIT
Figure 13.13 - EPP 1.9 Data or Address Write Cycle NAME t1 t2 t3 t4 t5 t6 t7 DESCRIPTION nWAIT Asserted to nWRITE Asserted (Note 1) nWAIT Asserted to nWRITE Change (Note 1) nWAIT Asserted to PDATA Invalid (Note 1) PDATA Valid to Command Asserted nWRITE to Command Asserted nWAIT Asserted to Command Asserted (Note 1) nWAIT Deasserted to Command Deasserted (Note 1) Command Asserted to nWAIT Deasserted Command Deasserted to nWAIT Asserted MIN 60 60 0 10 5 60 60 TYP MAX 185 185 UNITS ns ns ns ns ns ns ns
t7
t9
35 210 190 10
t8 t9
Note 1:
0 0
us ns
nWAIT must be filtered to compensate for ringing on the parallel bus cable. nWAIT is considered to have settled after it does not transition for a minimum of 50 nsec.
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t1 nWRITE t3 PD<7:0> t7 t8 t9 nDATASTB nADDRSTB t11 nWAIT
Figure 13.14 - EPP 1.9 Data or Address Read Cycle NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 DESCRIPTION nWAIT Asserted to nWRITE Deasserted nWAIT Asserted to nWRITE Modified (Notes 1,2) nWAIT Asserted to PDATA Hi-Z (Note 1) Command Asserted to PDATA Valid Command Deasserted to PDATA Hi-Z nWAIT Asserted to PDATA Driven (Note 1) PDATA Hi-Z to Command Asserted nWRITE Deasserted to Command nWAIT Asserted to Command Asserted nWAIT Deasserted to Command Deasserted (Note 1) PDATA Valid to nWAIT Deasserted PDATA Hi-Z to nWAIT Asserted MIN 0 60 60 0 0 60 0 1 0 60 TYP MAX 185 190 180
t2
t4
t5
t6
t10
t12
190 30 195 180
UNITS ns ns ns ns ns ns ns ns ns ns
t11 t12
Note 1: Note 2:
0 0
ns s
nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. When not executing a write cycle, EPP nWRITE is inactive high.
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t1 nWRITE t2 PD<7:0> t3 t4 nDATASTB nADDRSTB t5 nWAIT
Figure 13.15 - EPP 1.7 Data or Address Write Cycle NAME t1 t2 t3 t4 t5 DESCRIPTION Command Deasserted to nWRITE Change Command Deasserted to PDATA Invalid PDATA Valid to Command Asserted nWRITE to Command Command Deasserted to nWAIT Deasserted MIN 0 50 10 5 0 TYP MAX 40 UNITS ns ns ns ns ns
35 35
nWRITE t1 PD<7:0> nDATASTB nADDRSTB t3 nWAIT
Figure 13.16 - EPP 1.7 Data or Address Read Cycle NAME DESCRIPTION t1 Command Asserted to PDATA Valid t2 Command Deasserted to PDATA Hi-Z t3 Command Deasserted to nWAIT Deasserted MIN 0 0 0 TYP MAX UNITS ns ns ns
t2
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13.1
ECP Parallel Port Timing
13.1.1 Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to Figure 13.17.
13.1.2 ECP Parallel Port Timing
The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase.
13.1.3 Forward-Idle
When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low.
13.1.4 Forward Data Transfer Phase
The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest. The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in Figure 13.18. The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe).
13.1.5 Reverse-Idle Phase
The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low.
13.1.6 Reverse Data Transfer Phase
The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk. The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has been accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to accept a byte it sets HostAck (nALF) high to acknowledge the
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handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets HostAck (nALF) low, completing the transfer. This sequence is shown in Figure 13.19.
13.1.7 Output Drivers
To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used in ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-drain), the drivers are dynamically changed from open-drain to push-pull. The timing for the dynamic driver change is specified in then IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs.
t6 t3 PD<7:0> t1 t2 t5
nSTROBE
t4 BUSY
Figure 13.17 - Parallel Port FIFO Timing NAME t1 t2 t3 t4 t5 t6 Note 1: DESCRIPTION PDATA Valid to nSTROBE Active nSTROBE Active Pulse Width PDATA Hold from nSTROBE Inactive (Note 1) nSTROBE Active to BUSY Active BUSY Inactive to nSTROBE Active BUSY Inactive to PDATA Invalid (Note 1) MIN 600 600 450 TYP MAX UNITS ns ns ns ns ns ns
500 680 80
The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending. If no other data transfer is pending, the data is held indefinitely.
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t3 nALF t4 PD<7:0> t2 t1 t7 nSTROBE BUSY t6 t5 t6 t8
Figure 13.18 - ECP Parallel Port Forward Timing NAME DESCRIPTION t1 nALF Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nALF Changed (Notes 1,2) t4 BUSY Deasserted to PDATA Changed (Notes 1,2) t5 nSTROBE Asserted to Busy Asserted t6 nSTROBE Deasserted to Busy Deasserted t7 BUSY Deasserted to nSTROBE Asserted (Notes 1,2) t8 BUSY Asserted to nSTROBE Deasserted (Note 2) Note 1: Note 2: MIN 0 0 80 TYP MAX 60 60 180 UNITS ns ns ns
80 0 0 80 80
180
200 180
ns ns ns ns ns
Maximum value only applies if there is data in the FIFO waiting to be written out. BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
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t2 PD<7:0> t1 t5 nACK t4 nALF
Figure 13.19 - ECP Parallel Port Reverse Timing NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nALF Deasserted to PDATA Changed t3 nACK Asserted to nALF Deasserted (Notes 1,2) t4 nACK Deasserted to nALF Asserted (Note 2) t5 nALF Asserted to nACK Asserted t6 nALF Deasserted to nACK Deasserted Note 1: MIN 0 0 80 TYP MAX UNITS ns ns ns
t6
t3
t4
200 200
80 0 0
ns ns ns
Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nALF low. nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
Note 2:
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PCI_CLK t1 SER_IRQ
Figure 13.20 - Setup and Hold Time NAME t1 t2 DESCRIPTION SER_IRQ Setup Time to PCI_CLK Rising SER_IRQ Hold Time to PCI_CLK Rising MIN 7 0 TYP MAX UNITS nsec nsec
t2
Data Start TXD Data (5-8 Bits) t1 Parity Stop (1-2 Bits)
Figure 13.21 - Serial Port Data NAME t1 Note 1: DESCRIPTION Serial Port Data Bit Time MIN TYP tBR1 MAX UNITS nsec
tBR is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have percentage errors indicated in the "Baud Rate" table in the "Serial Port" section.
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KCLK/ MCLK t1
CLK CLK 1 2 t3 t4
t2 t6
CLK 9
CLK 10
CLK 11 t5
KDAT/ Start Bit MDAT
Bit 0
Bit 7
Parity Bit
Stop Bit
Figure 13.22 - Keyboard/Mouse Receive/Send Data Timing NAME t1 DESCRIPTION Time from DATA transition to falling edge of CLOCK (Receive) Time from rising edge of CLOCK to DATA transition (Receive) Duration of CLOCK inactive (Receive/Send) Duration of CLOCK active (Receive/Send) Time to keyboard inhibit after clock 11 to ensure the keyboard does not start another transmission (Receive) Time from inactive to active CLOCK transition, used to time when the auxiliary device samples DATA (Send) MIN 5 TYP MAX 25 UNITS sec
t2 t3 t4 t5 t6
5 30 30 >0 5
T4-5 50 50 50 25
sec sec sec sec sec
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t1 t2 FAN_TACHx
Figure 13.23 - Fan Tachometer Input Timing NAME t1 t2 t3 DESCRIPTION Pulse Time (1/2 Revolution Time=30/RPM) Pulse High Time Pulse Low Time MIN TYP 11.11 5.55 5.55 MAX UNITS sec sec sec
t3
t2 LED
t1
Figure 13.24 - Power Led Output Timing NAME t1 t2 DESCRIPTION MIN TYP 1.49 0.59 MAX UNITS sec sec
Period Blink ON Time
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3.3V
VCC/VTR
5V 3.3V
VCC5V/V_5P0_STBY
5V 3.3V 2.95V (min)
REF5V/REF5V_STBY
Figure 13.25 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Up Before VCC5V/ V_5P0_STBY Note:
The value 2.95V minimum in Figure 13.25 is (3.3 Supply Voltage - 350 mV).
3.3V
VCC/VTR
5V
VCC5V/V_5P0_STBY
5V
REF5V/REF5V_STBY
Figure 13.26 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Up Before VCC/VTR
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VCC/VTR
3.3V
VCC5V/V_5P0_STBY
5V
REF5V/REF5V_STBY
5V
Figure 13.27 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Down Before VCC5V/ V_5P0_STBY
VCC/VTR
3.3V
VCC5V/V_5P0_STBY
5V 3.3V
REF5V/REF5V_STBY
5V 3.3V 2.95V (min)
Figure 13.28 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Down Before VCC/VTR Note:
The value 2.95V minimum in Figure 13.28 is (3.3 Supply Voltage - 350 mV).
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A
Tpropr Tpropf
B
Tr Tf
Figure 13.29 - Rise, Fall and Propagation Timings
Table 13.1 - nIDE_RSTDRV Timing NAME Tf DESCRIPTION (Refer to Figure 13.29) nIDE_RSTDRV (B) high to low fall time. Measured form 90% to 10% nIDE_RSTDRV (B) high to low propagation time. Measured from nPCI_RESET (A) to nIDE_RSTDRV (B). Output Capacitance Load Capacitance MIN TYP MAX 15 UNITS ns
Tpropf CO CL
20 25 40
ns pF pF
Table 13.2 - nPCIRST_OUT and nPCIRST_OUT2 Timing NAME Tr DESCRIPTION (Refer to Figure 13.29) nPCIRST_OUT/nPCIRST_OUT2 (B) low to high rise time. Measured form 10% to 90% nPCIRST_OUT/nPCIRST_OUT2 (B) low to high propagation time. Measured from nPCI_RESET (A) to nPCIRST_OUT/nPCIRST_OUT2 (B). Output Capacitance Load Capacitance Table 13.3 - PS_ON Timing NAME Tz Tf DESCRIPTION (Refer to Figure 13.29) nPS_ON (B) low to Hi-Z rise time. nPS_ON (B) high to low fall time. Measured form 90% to 10% nPS_ON (B) low to Hi-Z propagation time. Measured from nSLP_S3 (A) to nPS_ON (B). nPS_ON (B) high to low propagation time. Measured from nSLP_S3 (A) to nPS_ON (B). Output Capacitance Load Capacitance MIN TYP MAX 50 50 UNITS ns ns MIN TYP MAX 53 UNITS ns
Tpropr
30
ns
CO CL
25 40
pF pF
Tpropz Tpropf CO CL
1 1 25 50
us us pF pF
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Table 13.4 - SCK_BJT_GATE Timing NAME Tf DESCRIPTION (Refer to Figure 13.29) SCK_BJT_GATE (B) low to high fall time. Measured form 90% to 10% SCK_BJT_GATE (B) high to low propagation time. Measured from PWRGD_3V (A) to SCK_BJT_GATE (B). Output Capacitance Load Capacitance Table 13.5 - PWRGD_3V Timing NAME Tr Tf DESCRIPTION (Refer to Figure 13.29) PWRGD_3V (B) low to high rise time. PWRGD_3V (B) low to high fall time. Measured form 90% to 10% PWRGD_3V (B) low to high propagation time. Measured from nFPRST (A) to PWRGD_3V (B). PWRGD_3V (B) high to low propagation time. Measured from nFPRST (A) to PWRGD_3V (B). Output Capacitance Load Capacitance MIN TYP MAX 50 50 UNITS ns ns MIN TYP MAX 50 UNITS ns
Tpropf
1
us
CO CL
25 50
pF pF
Tpropr Tpropf CO CL
1 1 25 50
us us pF pF
Table 13.6 - CNR CODEC Down Enable Timing NAME Tr DESCRIPTION (Refer to Figure 13.29) nCDC_DWN_RST (B) rise time. Measured from 10% to 90%. nCDC_DWN_RST (B) fall time. Measured from 90% to 10%. nCDC_DWN_RST (B) low to high propagation delay. Measured from nAUD_LNK_RST (A) or nCDC_DWN_ENAB (A) to nCDC_DWN_RST (B). nCDC_DWN_RST (B) high to low propagation delay. Measured from nAUD_LNK_RST (A) or nCDC_DWN_ENAB (A) to nCDC_DWN_RST (B). MIN TYP MAX
6 6 15.3
UNITS us
Tf Tpropr
us ns
Tpropf
15.3
ns
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VTR (3.3V) t3 V_5P0_STBY
Max Vtrip Min
t4
t1 nRSMRST
t2
Figure 13.30 - Reseme Reset Sequence Table 13.7 - Resume Reset Timing NAME t1 DESCRIPTION Treset delay. V_5P0_STBY active to nRSMRST inactive MIN 10 TYP 32 MAX 100 UNITS msec Notes 1
t2
t3 t4 VTRIP
Note 1:
Treset_fall. V_5P0_STBY inactive to nRSMRST active (Glitch width allowance) Treset_rise V_5P0_STBY active to VTR active V_5P0_STBY inactive to VTR inactive V_5P0_STBY low trip voltage
100 100 0 0 4.2
nsec nsec msec msec V
4.5
2 2 3
The nRSMRST will be inactive high max 100 msec after V_5P0_STBY is active assuming the VTR (3.3V) is active. If the VTR (3.3V) is not active within 100 msec, the delay from V_5P0_STBY will be greater than 100 msec and the nRSMRST will go inactive when VTR (3.3V) goes active. The V_5P0_STBY supply must power up before or simultaneous with VTR, and must power down simultaneous with or after VTR (from ICH2 data sheet) The trip point can vary between these limits on a per part basis, but on a given part it should remain relatively stable.
Note 2:
Note 3:
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Chapter 14 Package Outline
Figure 14.1 - 128 Pin MQFP Package Outline, 14x20x2.7 Body, 3.2mm Footprint MIN ~ 0.05 2.55 23.00 19.90 17.00 13.90 0.09 0.73 ~ Table 14.1 - 128 Pin MQFP Package Parameters NOMINAL MAX REMARKS ~ 3.4 Overall Package Height ~ 0.5 Standoff ~ 3.05 Body Thickness 23.20 23.40 X Span 20.00 20.10 X body Size 17.20 17.40 Y Span 14.00 14.10 Y body Size ~ 0.20 Lead Frame Thickness 0.88 1.03 Lead Foot Length 1.60 ~ Lead Length 0.50 Basic Lead Pitch ~ 7o Lead Foot Angle ~ 0.30 Lead Width ~ ~ Lead Shoulder Radius ~ 0.30 Lead Foot Radius ~ 0.08 Coplanarity
A A1 A2 D D1 E E1 H L L1 e W R1 R2 ccc Notes:
1. 2. 3. 4. 5.
0o 0.10 0.08 0.08 ~
Controlling Unit: millimeter. Tolerance on the position of the leads is 0.04 mm maximum. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. Details of pin 1 identifier are optional but must be located within the zone indicated.
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Chapter 15 Board Test Mode
Board level testing is implemented with an XOR Chain. The XOR chain testing allows motherboard manufacturers to check component connectivity (e.g., opens and shorts to VCC or GND). The TEST_EN pin is used as a strap pin to enter test mode. This pin has an internal 30 A pull-down resistor to VSS. An external 10 kohm pull-up to V_3P3_STBY is used to put the device in test mode. Both VCC and VTR supplies are required for the device to operate properly in test mode. The part enters board test (XOR-chain) mode when the TEST_EN pin is brought high. The part remains in test mode while TEST_EN is high. Bringing TEST_EN low will exit test mode. When the XOR chain is entered, all output and bi-directional buffers within that chain are tri-stated, except for the XOR chain output. Every signal in the XOR chain (except for the XOR chain's output) functions as an input. Figure 15.1 is a schematic example of XOR chain circuitry.
VCC3
Input Pin 1
Input Pin 2
Input Pin 3
Input Pin 4
Input Pin 5
XOR Chain Output
Figure 15.1 - Example XOR Chain Circuitry
The XOR chain output is on pin 30, nDTR1/XOR. The input pin ordering is as follows: the first input pin in the XOR chain is pin 1 of the chip (MCLK), and the order continues around the chip in increasing pin number order to end at pin 128, skipping those pins that are excluded from the chain. The following pins are excluded from the XOR chain. nRSMRST pin (1) REF5V pin (1) REF5V_STBY pin (1) VCC pins (5) VTR pins (4) V_5P0_STBY pin (1) VSS pins (7) F_CAP pin (1) nDTR1/XOR pin (1) TEST_EN pin (1) The total number of pins excluded from the XOR chain is 23; therefore there are an odd number of pins in the XOR chain.
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XOR Chain Testability Algorithm Example An example algorithm for using the XOR chain for board test is shown below.
Table 15.1 - XOR Test Pattern Example TEST VECTOR INPUT PIN 1 0 1 1 1 1 1 INPUT PIN 2 0 0 1 1 1 1 INPUT PIN 3 0 0 0 1 1 1 INPUT PIN 4 0 0 0 0 1 1 INPUT PIN 5 0 0 0 0 0 1 XOR OUTPUT
1 2 3 4 5 6
1 0 1 0 1 0
In this example, Vector 1 applies all "0s" to the chain inputs. The outputs being non-inverting, will consistently produce a "1" at the XOR output on a good board. One short to VCC (or open floating to VCC) will result in a "0" at the chain output, signaling a defect. Likewise, applying Vector 6 (all "1s") to the chain inputs (given that there is an odd number of input signals in the chain) will consistently produce a "0" at the XOR chain output on a good board. One short to VSS (or open floating to VSS) will result in a "1" at the chain output, signaling a defect. It is important to note that the number of inputs pulled to "1" will affect the chain output value. If the number of chain inputs pulled to "1" is even, then a "1" will be seen at the output. If the number of chain inputs pulled to "1" is odd, a "0" will be seen at the output. Continuing with the example in Table 15.1, as the input pins are driven to "1" across the chain in sequence, the XOR Output will toggle between "0" and "1." Any break in the toggling sequence (e.g., "1011") will identify the location of the short or open.
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Chapter 16 Reference Documents
1. 2. 3. 4. 5. 6. 7. 8. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997. Low Pin Count (LPC) Interface Specification, Revision 1.0, September 29, 1997, Intel Document. Metalious ACPI/Manageability Specification, v1.0, Aril 30, 1999 Advanced Configuration and Power Interface Specification, v 1.0 SMSC Application Note, AN 8-8: Using the Enhanced Keyboard and Mouse Wakeup Feature in SMSC Super I/O Parts. SMSC Application Note, AN 9-3: Application Considerations When Using the Powerdown Feature of SMSC Floppy Disk Controllers.
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